CYNSE10128-083FGCI CYPRESS [Cypress Semiconductor], CYNSE10128-083FGCI Datasheet - Page 133

• Manufacturer Part Number: CYNSE10128-083FGCI
• Manufacturer: CYPRESS [Cypress Semiconductor]

6.8
Table 6-14 shows the idle cycle requirements between operations. The operations in the second column represent operations
already performed, and the operations in the first row are those we would like to perform next.
Example calculations:
Table 6-14. Required Idle Cycles Between Commands
Notes:
Document #: 38-02069 Rev. *F
15. When the register being read is SSR/SRR and it matches the target location of the previous search, a READ operation cannot be issued for 2+TLSZ idle cycles
16. In Non-Enhanced Mode there is no idle cycle requirement. In Enhanced Mode, an SRR is updated on a SEARCH miss and is used as the address for the
17. The SRAM operation needs to insert idle cycles to avoid SADR bus contention with previous SEARCH.
18. In non-Enhanced Mode, a WRITE operation updates the NFA register used for LEARN operation. Must wait for 1+TLSZ cycles before issuing LEARN to avoid
19. If the Learn is issued 2+TLSZ after the corresponding Search that updated the SRR, the Learn will be issued before the Search result or the updated FULL
1. Read after Write: The Write takes two 2 cycles, and one 1 idle cycle is required. Thus if the Write is issued in cycle 1, the Read
2. Learn from SRR after Search x288, with TLSZ=10 (binary): The Search takes 2 cycles, and (2+TLSZ) idle cycles are required.
cannot be issued until cycle 4. Note, all cycles after an SRAM Read or an NSE Read (blocking) operation are considered
blocked until the ACK signal is returned.
Thus if the Search is issued in cycle 1, the Learn cannot be issued until cycle 7.
to avoid reading the old value. Otherwise there is no idle cycle requirement.
LEARN. Must wait for 2+TLSZ cycles after the last Search, before issuing a subsequent Learn that uses the same SRR as the last Search.
learning with the old NFA value.
signal is returned. If the Search resulted in a hit, the Learn will be suppressed. If there was a miss, but the device is already full, the Learn will also be suppressed.
x72/x144 = 1 Cycle
x72/x144 = 1 Cycle
x288 = 2 Cycles
x576 = 4 Cycles
x288 = 2 Cycles
x576 = 4 Cycles
# of Cycles
Timing Sequences for Back-to-Back Operations
2 Cycles
2 Cycles
1 Cycle
1 Cycle
SADR[M:0]
CMD[10:2]
CMD[1:0]
CLK2X
PHS_L
ALE_L
CMDV
WE_L
OE_L
CE_L
ACK
SSV
SSF
TLSZ = 10 (binary), HLAT = XXX, LRAM = 1 (binary), LDEV = 1 (binary)
M = 25 for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128
DQ
Figure 6-76. SRAM Write Through Device #30 in Bank of 31 Devices
OPERATIONS
SRAM WRITE
SRAM READ
SEARCH
WRITE
LEARN
1
1
1
0
0
z
0
READ
Address
cycle
Write
1
A B
01
5+TLSZ+HLAT 5+TLSZ+HLAT 5+TLSZ+HLAT 5+TLSZ+HLAT 5+TLSZ+HLAT
cycle
SEARCH
No Wait
2
CONFIDENTIAL
x
PRELIMINARY
5
1
1
1
cycle
3
x
cycle
4
No Wait /
2+TLSZ
cycle
READ
5
5
1
1
1
cycle
6
15
cycle
7
No Wait
WRITE
cycle
5
1
1
1
8
cycle
1
9
z
z
z
z
1 / 1+TLSZ
2+TLSZ
cycle
No Wait /
10
LEARN
5
1
1
16,19
0
1
1
1
CYNSE10512
CYNSE10256
CYNSE10128
18
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2+TLSZ
SRAM
TLSZ /
5
1
1
1
17
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