CYNSE10128-083FGCI CYPRESS [Cypress Semiconductor], CYNSE10128-083FGCI Datasheet - Page 121

• Manufacturer Part Number: CYNSE10128-083FGCI
• Manufacturer: CYPRESS [Cypress Semiconductor]

6.7
SRAM Read enables read access to the off-chip SRAM containing associative data. The latency from the issuance of the Read
instruction to the appearance of the address on the SRAM bus is the same as the Search instruction latency, and will depend on
the value programmed for the TLSZ parameter in the device configuration register. The latency of the ACK from the Read
instruction is the same as that from the Search instruction to the SRAM address latency, plus the HLAT programmed in the
configuration register. Note. SRAM Read is a blocking operation—no new instruction can begin until the ACK is returned by the
selected device performing the access.
SRAM Write enables write access to the off-chip SRAM containing associative data. The latency from the second cycle of the
Write instruction to the appearance of the address on the SRAM bus is the same as the Search instruction latency, and will depend
on the TLSZ value parameter programmed in the device configuration register. Note: SRAM Write is a pipelined operation—new
instruction can begin right after the previous command has ended.
6.7.1
SRAM Read enables read access to the off-chip SRAM containing associative data. The latency from the issuance of the Read
instruction to the appearance of the address on the SRAM bus is the same as Search instruction latency, and will depend on the
TLSZ value parameter programmed into the device configuration register. ACK latency from the Read instruction is the same as
that from the Search instruction to the SRAM address, plus the HLAT programmed in the configuration register. The following
explains the SRAM Read operation in a table with only one device that has the following parameters: TLSZ = 00 (binary), HLAT =
000 (binary), LRAM = 1 (binary), and LDEV = 1 (binary). Figure 6-63 shows the associated timing diagram. For the following
description, the selected device refers to the only device in the table because it is the only device to be accessed.
At the end of cycle 6, the selected device floats ACK in a three-state condition, and a new command can begin.
Document #: 38-02069 Rev. *F
• Cycle 1A: The host ASIC applies the Read instruction on CMD[1:0] using CMDV = 1 (binary). The DQ bus supplies the address,
• Cycle 1B: The host ASIC continues to apply the Read instruction on CMD[1:0] using CMDV = 1 (binary). The DQ bus supplies
• Cycle 2: The host ASIC floats DQ[71:0] to a three-state condition.
• Cycle 3: The host ASIC keeps DQ[71:0] in a three-state condition.
• Cycle 4: The selected device starts to drive DQ[71:0] and drives ACK from High-Z to LOW.
• Cycle 5: The selected device drives the Read address on SADR[N:0] lines (N = 25 for CYNSE10512, 24 for CYNSE10256,
• Cycle 6: The selected device drives CE_L HIGH, ALE_L HIGH, the SADR bus, the DQ bus in a three-state condition, and
with DQ[20:19] set to 10 (binary), to select the SRAM address. The host ASIC selects the device for which ID[4:0] matches
the DQ[25:21] lines. During this cycle, the host ASIC also supplies SADR[25:23] for CYNSE10512, SADR[24:22] for
CYNSE10256, SADR[23:21] for CYNSE10128 on CMD[8:6].
the address with DQ[20:19] set to 10 to select the SRAM address.
23 for CYNSE10128) and drives ACK HIGH, CE_L LOW, and ALE_L LOW.
ACK LOW.
SRAM PIO Access
SRAM Read with a Table of One Device
CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Page 121 of 153
[+] Feedback
[+] Feedback