CYNSE10128-083FGCI CYPRESS [Cypress Semiconductor], CYNSE10128-083FGCI Datasheet - Page 84

• Manufacturer Part Number: CYNSE10128-083FGCI
• Manufacturer: CYPRESS [Cypress Semiconductor]

The logical 144-bit Search operation is shown in Figure 6-30. The entire table of 31 devices (consisting of 72-bit entries) is
compared to a 144-bit word K presented on the DQ bus in both cycles A and B of the command using the GMR and local mask
bits. The GMR is the 144-bit word specified by the even and odd GMR pairs selected by the GMR index in the command’s cycle
A. The 144-bit word K (presented on the DQ bus in both cycles A and B of the command) is also stored in both even and odd
comparand register pairs selected by the comparand register index in command cycle B. In the ×144 configuration, the even and
odd comparand register can be subsequently used by the Learn command only in the first non-full device.
Note. The Learn command is supported for only one of the blocks consisting of up to eight devices in a depth-cascaded table of
more than one block.
The word K (presented on the DQ bus in both cycles A and B of the command) is compared with each entry in the table, starting
at location 0 (decimal). A matching entry that satisfies the Soft Priority and Mini-Key scheme (for Enhanced Mode) will be the
winning entry, and its location address L will be driven as part of the SRAM address on the SADR[N:0] lines (see “SRAM PIO
Access” on page 121), N = 25 for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128. The global winning device will drive
the bus in a specific cycle. On global miss cycles, the device with LRAM = 1 (binary) and LDEV = 1 (binary) will be the default
driver for such missed cycles.
Note. During 144-bit searches of 144-bit-configured tables, the Search hit will always be at an even address.
The Search command is a pipelined operation and executes a Search at half the rate of the frequency of CLK2X for 144-bit
searches in ×144-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 144-bit Search
command cycle (two CLK2X cycles) is shown in Table 6-4.
For up to 31 devices in the table (TLSZ = 10 (binary)), Search latency is 6 from command to SRAM access cycle. In addition,
SSV and SSF shift further to the right for different values of HLAT, as specified in Table 6-5.
Document #: 38-02069 Rev. *F
— DQ Bus: The DQ[71:0] continues to carry the 72-bit data to be compared.
during cycles A and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address
of the matching entry and the hit flag (see page 27 for the description of SSR[0:7]). CMD[10:9] are don’t cares in this cycle.
Must be same in each of the 31
Will be same in each of the 31
Comparand Register (odd)
Comparand Register (even)
71
devices
devices
A
B
Figure 6-30. ×144 Table with 31 Devices
0
CONFIDENTIAL
PRELIMINARY
Location
address
GMR
N
L
0
2
4
6
K
143
143
(144-bit configuration)
Even
A
Odd
B
0
0
(First matching entry)
N = 4063231 for CYNSE10512
2031615 for CYNSE10256
1015807 for CYNSE10128
CYNSE10512
CYNSE10256
CYNSE10128
Page 84 of 153
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