CYNSE10128-083FGCI CYPRESS [Cypress Semiconductor], CYNSE10128-083FGCI Datasheet - Page 152

• Manufacturer Part Number: CYNSE10128-083FGCI
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document History Page
Document #: 38-02069 Rev. *F
Document Title: CYNSE10512/CYNSE10256/CYNSE10128 Ayama 10000 Network Search Engine
Document Number: 38-02069
REV.
*A
*B
*C
*D
**
119954 01/16/03
123910 02/13/03 KHS for
126318 05/09/03
129255 10/08/03
205841
ECN
NO.
Issue
Date
Change
Orig. of
XBM
BGT
KHS
KHS
ITL
New Data Sheet
Added the following information:
32 CLK2X cycles wait after a write to COMMAND register
Enhanced mode Block configuration (in BMR) prior to entries initialization
Blocks initialization prior to accessing the blocks
Clarification on static signals voltage level
External pull-up resistor requirement for PARERR_L signal
Section 5.1.2.3: PARERR changed to Active-Low PARERR_L
Updated the timing of PARERR_L signal validity
Section 5.3.14: Updated SRR’s PRIORITY field definition for when Search operation
resulted in a miss
Section 5.12: Modified the statement on how to control TRST_L
Section 6.2: Fixed Learn Command B-cycle Bit[7] on Enhanced Mode for x288/x576 from
‘X’ to ‘0’
Figure 6.3: Updated PARERR_L signal valid per Section 5.1.2.3 update
Figure 6-6 and 6-8: SSV to reflect idle cycles on 288-bit searches
Section 6.6: Note on mismatched entry width Learn operation
Figure 6-57, 6-58 and 6-59: Added ALE_L signal
Section 11 and Section 12: Added package orientations
Figure 11-1 and Table 11-1: Pin AA24 changed from VDDQ_SRAM to VDD
Table 4-1: Added CFG_L signal and description (signal is bonded out to B24)
Table 4-1: Corrected the DQ direction to I/O
Section 4.0, Note 4: Updated PARERR_L pull-up resistance recommendation
Table 4-1: Corrected PAR[1:0] direction to I/O
Table 4-1: Updated HIGH_SPEED1 and HIGH_SPEED2 description
Table 4-1: Corrected polarity mode of FULI[6:0] and FULO[1:0]
Section 5.1.2.3: Updated description of Parity feature
Figure 5-4; Figure 5-5: Added timing diagrams of DQ and Core Parity error
Section 5.1.2.4: Corrected description of CLK2x
Section 5.4.1: Clarify CMPR registers width
Section 5.4.2: Clarify GMR registers width
Table 5-5: Renamed register name from Status to Successful and updated INDEX field
Figure 5-11, Table 5-6: Removed READ bit. It is now RESERVED.
Table 5-8 and 5-9: Replaced ADR with INDEX
Table 5-12: Updated Hardware register fields
Table 5-13: Update ADR description
Table 5-17: Corrected Minikey3 range
Table 5-20: Clarify F3 field description
Table 5-26: Corrected INDIRECT description
Section 5.10.1: Corrected typo on 64K x 288
Section 6.2.1-3: Replaced SADR with EADR, added note
Section 6.3.2: Added to description of Burst Read
Table 6-3: Corrected typos
Section 6.4.2: Added to description of Burst Write
Section 6.4.3: Added to description of Parallel Write
Figure 6-15: Rewording on one of the notes
Section 6-6: Added explanation of blind Learn and Learn suppression.
Figure 6-56/57: Added timing diagrams for x72 and x288 Learn
Section 6.8: Added section on Timing Sequences for Back-to-Back Operations
Section 6.9: Added section on FULL signal: description and timing diagram
Section 9.0: Added Maximum Ratings data and rearranged the parameters
Table 10-1: Updated the descriptions of the timing parameters and notes
Figure 10-1: Added PHS_L and clarify boundaries of parameters
Figure 10-2: Clarify boundaries of parameters
Table 11-1: Added CFG_L to Pin List and removed DQ[72]
Minor Change: Upload MPN to external website
CONFIDENTIAL
PRELIMINARY
Description of Change
CYNSE10512
CYNSE10256
CYNSE10128
Page 152 of 153
[+] Feedback
[+] Feedback