CYNSE10128-083FGCI CYPRESS [Cypress Semiconductor], CYNSE10128-083FGCI Datasheet - Page 153

• Manufacturer Part Number: CYNSE10128-083FGCI
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-02069 Rev. *F
Document Title: CYNSE10512/CYNSE10256/CYNSE10128 Ayama 10000 Network Search Engine
Document Number: 38-02069
REV.
*E
*F
212292
239580
ECN
NO.
Issue
Date
ECN
ECN
See
See
Change
Orig. of
DCU
KHS
p10: 576-bit configuration is supported in Enhanced Mode only
p15-p17, Table 4-1: General signal description clarification
p27, Figure 5-9: Added addresses value of the GMR Registers
p28, Table5-4: GVAL is valid only in Enhanced Mode
p29, Table 5-5: Clarified operations that are affected by HLAT
p33, Table 5-11: Corrected locations of the IO Interfaces control bits and drive strengths
p41, Section 5.6: Clarified phase cycles of CLK2X
p42, Figure 5-27, 5-28, 5-29: Added cycle A and cycle B references to diagrams
p43, Table 5-24: Clarified operating speed clock references
p48, Section 5.11: Clarified description of indirect read
p50, Section 6.1: Clarified cycle A, cycle B descriptions relative to command encoding
p53, Figure 6-2: Changed EOT low cycle time
p95, Section 6.5.8: Removed redundant note on Multisearch
p113-114, Section 6.6: Clarified Learn description
p115, Figure 6-57: Corrected timing diagram to add a cycle between commands
p116, Figure 6-58: Added 576-bit Learn DQ timing diagram
p117, Figure 6-59: Added 576-bit Learn CMPR timing diagram
p121-p133, Various: Corrected SRAM operation timing diagram
p133, Section 6-8: Added examples of back-to-back operations
p133, Note 16: Clarified note description
p133, Note 19: New note on Learn operation
p136, Section 9.0: Modified storage temperature range and Latch-Up Current rating
p136-p137, Table 9-1 part 1: Expanded Standby and Operating current parameters
p137, Table 9-1 part 2: Added Load Capacitance for CMD bus
p137, Table 9-2: Added Commercial and Industrial ambient temperature ranges
p138, Table 10-1: Updated the following parameters: fCLOCK, tIHCH, tICHCH, tCKHDV,
tCKHSV, tCKHDZ, tCKHSHZ, tISCH
p139, Figure 10-1: Added FULL, PAR, MULTI_HIT
p140, Table 10-2: Updated the following parameters: fCLOCK, tIHCH, tICHCH, tCKHDV,
tCKHSV, tCKHDZ, tCKHSHZ, tISCH
p141, Figure 10-2: Added FULL, PAR, MULTI_HIT
p142, Figure 10-4, 10-5, 10-6: Updated diagrams to best represent actual test condition
p143, Figure 10-8, 10-9, 10-10: Updated diagrams to best represent actual test condition
p149, Table 11-1: Added notes to identify pins that are not valid for smaller densities
Other:
Removed all references to cascade performance.
p134, Figure 6-77: Added diagram for Non-Enhanced mode FULL, corrected TLSZ error
p140, Figure 10-1: Added signal group for MultiSearch operation timing, clarified cycle
relationship
p138, Table 10-1: Expanded CLK2X AC timing parameters table for cascade signals,
added minimum pulse width for RST_L
p139, Table 10-2: Expanded CLK1X AC timing parameters table for cascade signals,
added minimum pulse width for RST_L
p142, Figure 10-2: Added signal group for MultiSearch operation timing, clarified cycle
relationship, removed reference to internal clock
p49, Figure 5-35: Clarified power-up sequence figure and description
p15, Table 4-1: Clarified cycle timing for device activation after RST_L
p141, Table 10-3: Added JTAG AC Timing Table
p137, Table 9-1: Removed table cells and replaced with a note
p55, Section 6.4.3: Clarified Parallel write description
CONFIDENTIAL
PRELIMINARY
Description of Change
CYNSE10512
CYNSE10256
CYNSE10128
Page 153 of 153
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