CYNSE10128-083FGCI CYPRESS [Cypress Semiconductor], CYNSE10128-083FGCI Datasheet - Page 114

• Manufacturer Part Number: CYNSE10128-083FGCI
• Manufacturer: CYPRESS [Cypress Semiconductor]

Note that Learn command for x144 entry width in Non-Enhanced can only be issued when all the tables in the device is of x144
table width.
6.6.2
The Learn command in the Enhanced mode supports all table widths (x72, x144, x288 and x576). The user can select whether
the data stored in the user selected CMPR register or the data presented in the DQ bus be used for the learn operation. The user
can also select to write to an entry in either the Data or Mask array. The address for the target entry is the INDEX field of the user-
selected Search Result Register (SRR). Each SRR is one-to-one associated to a Comparand (CMPR) register. So the selection
of the SRR is accomplished by selecting the corresponding (CMPR) register.
The SRR register is updated after a Search operation. Only the LSB of each entry is used, regardless of width, to indicate whether
that entry is free (=0 (binary)) or not (=1 (binary)).
Document #: 38-02069 Rev. *F
TLSZ = 00 (binary), LRAM = 1 (binary), LDEV = 1 (binary).
Enhanced Mode
SADR[M:0]
Figure 6-56. Timing Diagram of 72-bit Learn from DQ Bus and CMPR Registers (One Device)
CMD[1:0]
CMD[5:2]
CMD[10]
CLK2X
PHS_L
CMDV
ALE_L
CMD[9]
WE_L
OE_L
CE_L
SSV
SSF
DQ
Learn Data
Learn from DQ
1
1
1
0
0
0
cycle
CMPR
1
Learn
x72
a
cycle
CONFIDENTIAL
PRELIMINARY
2
cycle
CMPR
3
Learn
b
cycle
Learn Mask
Learn from CMPR
M = 25 for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128
4
cycle
5
cycle
1
6
A1
0
0
0
cycle
7
cycle
8
cycle
9
cycle
10
1
1
CYNSE10512
CYNSE10256
CYNSE10128
0
Page 114 of 153
[+] Feedback
[+] Feedback