CYNSE10128-083FGCI CYPRESS [Cypress Semiconductor], CYNSE10128-083FGCI Datasheet - Page 22

• Manufacturer Part Number: CYNSE10128-083FGCI
• Manufacturer: CYPRESS [Cypress Semiconductor]

PARERR_L
5.1.2.4 MultiSearch
When MultiSearch is activated, the Core is divided into two separate arrays. Each array is organized into 64/32/16 blocks
(corresponds to CYNSE10512/CYNSE10256/CYNSE10128, respectively) of 2K 72-bit entries. Each block can be configured to
be of width x72, x144, x288, or x576. This separation allows a Search operation to simultaneously perform the search across
both arrays. The output signals will run at double data rate to effectively increase the throughput to a maximum of 266 million
searches per second. Each array can have multiple tables with different widths. Single-Search operation outputs are driven at
the rising edge of CLK1X. When the device has the MultiSearch feature enabled and MultiSearch operation is issued (Single-
Search can still be issued even when MultiSearch is enabled), the output is driven at both rising and falling edges of CLK1X
(rising edge of CLK2X). Output from Array 0 is driven at the rising edge while output from Array 1 is driven at the falling edge of
CLK1X. Figure 5-6 shows an illustration of the MultiSearch operation.
Both arrays will use the same Search key except for search operation on 72-bit wide tables. So does the selection of the Global
Mask Register (GMR) and Comparand Register (CMPR) as listed in Table 5-2.
Document #: 38-02069 Rev. *F
CMD[10:2]
CMD[1:0]
PHS_L
CLK2X
CMDV
DQ
cycle
A
PARITY
READ
1
T
B
cycle
2
Figure 5-5. Timing Diagram of a Core Parity Error (TLSZ=00)
SEARCH
T+1
cycle
Figure 5-6. MultiSearch Operation Overview
3
T+2
x72
x72
x576
cycle
CONFIDENTIAL
PRELIMINARY
4
RESULT0 RESULT1
Array 0
T+3
cycle
Time
5
T+4
x72
x144
cycle
x288
6
Array 1
T+5
cycle
7
cycle
8
cycle
9
CYNSE10512
CYNSE10256
CYNSE10128
Page 22 of 153
cycle
10
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