CYNSE10128-083FGCI CYPRESS [Cypress Semiconductor], CYNSE10128-083FGCI Datasheet - Page 47

• Manufacturer Part Number: CYNSE10128-083FGCI
• Manufacturer: CYPRESS [Cypress Semiconductor]

5.10.2
Figure 5-33 shows the cascading of up to four blocks. Each block except the last contains up to eight Ayama 10000 devices, and
the interconnection within each with the cascading of up to eight devices in a block was shown in the previous subsection.
Note. The interconnection between blocks for depth cascading is important. For each Search, a block asserts BHO[2], BHO[1],
and BHO[0]. The BHO[2:0] signals for a block are taken only from the last device in that block. For all other devices within that
block, these signals stay open. The host ASIC must program TLSZ to 10 (binary) in each of the devices for cascading up to 31
devices (in up to four blocks).
5.10.3
Bit[0] of each of the 72-bit entries is designated as a special bit (1 = occupied, 0 = empty). For each Learn or PIO Write to the
data array, each device asserts FULO[1] or FULO[0] depending on whether or not it has any empty locations within it (see
Figure 5-34). Each device combines the FULO signals from the devices above it with its own full status to generate a FULL signal
that gives the full status of the table up to the device asserting the FULL signal. Figure 5-34 shows the hardware connection
diagram for generating the FULL signal that goes back to the ASIC. In a depth-cascaded block of up to eight devices, the FULL
signal from the last device should be fed back to the ASIC controller to indicate the fullness of the table. The FULL signal of the
other devices should be left open. Note. The Learn instruction is supported for only up to eight devices, whereas FULL cascading
is allowed only for one block in tables containing more than eight devices. In tables for which a Learn instruction is not going to
be used, the bit[0] of each 72-bit entry should always be set to 1.
Document #: 38-02069 Rev. *F
Depth Cascading up to 31 Devices in 4 Blocks
Depth Cascading for a FULL Signal
SSF, SSV
DQ[71:0]
CMD[10:0], CMDV
Figure 5-33. Depth Cascading 4 Blocks
BHO[2]
BHO[2]
BHI[2]
CONFIDENTIAL
BHO[2]
BHO[2]
Block of 8 Ayama 10000s Block 2
Block of 7 Ayama 10000s Block 3
Block of 8 Ayama 10000s Block 0
Block of 8 Ayama 10000s Block 1
PRELIMINARY
BHI[2]
BHI[2]
BHI[2]
(devices 16–23)
(devices 24–30)
(devices 8–15)
(devices 0–7)
BHO[1]
BHO[1]
BHI[1]
BHO[1]
BHO[1]
BHI[1]
BHI[1]
BHI[1]
BHO[0]
BHO[0]
BHO[0]
BHO[0]
BHI[0] GND
BHI[0]
BHI[0]
BHI[0] GND
GND
SRAM
CYNSE10512
CYNSE10256
CYNSE10128
Page 47 of 153
[+] Feedback
[+] Feedback