CYNSE10128-083FGCI CYPRESS [Cypress Semiconductor], CYNSE10128-083FGCI Datasheet - Page 60

• Manufacturer Part Number: CYNSE10128-083FGCI
• Manufacturer: CYPRESS [Cypress Semiconductor]

Note. For 72-bit searches, the host ASIC can supply different 72-bit data on DQ[71:0] during both cycles A and B to be compared
with the tables in array 0 and 1 of the data array. The even and odd pairs of GMRs selected for the comparison need not be
programmed with the same value. For 144-bit, 288-bit or 576-bit searches, each 72-bit presented on each cycle A and B will
together form the 144-bit or 288-bit or 576-bit search key respectively. These search keys are compared to both array 0 and 1
during cycles A and B.
When an N-bit search key, K, is presented on the DQ bus, both arrays of N-bit entries are compared to the search key using the
GMR and local mask bits. The GMR is selected by the GMR Index in the command’s cycle A. K is also stored in both even and
odd comparand register pairs (selected by the comparand register index in command cycle B). K is compared with each entry in
the table, starting at location 0. A matching entry from each array that satisfies the Soft Priority and Mini-Key scheme will be the
winning entries, and their location addresses La and Lb will be driven as part of the SRAM address on the SADR[N:0] lines (see
Section 6.7, “SRAM PIO Access,” on page 121), N = 25 for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128.
The latency of the Search from command to SRAM access cycle is 5 for a single device (or up to eight devices) configuration in
the table (TLSZ[1:0] = 01). SSV and SSF also shift further to the right for different values of HLAT, as specified in Table 6-5.
Figure 6-8 shows a multiwidth configuration when multisearch is enabled using CYNSE10512 as an example.
The NES field in the Block Mini-Key Register (BMR) should be configured as follows:
6.5.3
The hardware diagram of the Search subsystem of up to eight devices is shown in Figure 6-9. The MultiSearch Mode (MSE) bit
in the Command Register must be set LOW to perform single-search. The following are the rest of the parameters programmed
into the eight devices.
Note: The device receiving all the LHO signals from the other devices is the last device.
For a single-device configuration, the parameters are the same as device 7. BHI[2:0] and LHI[6:0] should be tied to ground.
Document #: 38-02069 Rev. *F
• Cycle B:
• For the first 32 blocks in the data array, NES = 00 (binary) for 72-bit table width. For the next 16 blocks, NES = 01 (binary) for
• Setting NES = 00 (binary) for the next 32 blocks will configure those blocks to be 72-bit table in array 1. Setting NES = 01
• In Non-Enhanced Mode, first seven devices (devices 0–6) must reset all bits of the CFG field in Configuration register to zeroes.
• In Non-Enhanced Mode, the eighth device (device 7) should still reset all bits of the CFG field in Configuration register to
144-bit table width. For the following 16 blocks, NES = 10 (binary) for 288-bit table width. These will configure the tables in array 0.
(binary) for the next 16 blocks will configure those blocks to be 144-bit table. Setting the final 16 blocks’ NES field will configure
those blocks to be 288-bit table.
In Enhanced Mode, these devices should have the NES field of each block within a device configured to 00 for 72-bit table
width. TLSZ = 01 (binary), HLAT = 010 (binary), LRAM = 0 (binary), and LDEV = 0 (binary) for both modes.
zeroes. In Enhanced Mode, NES should still be 00 (binary). But TLSZ = 01 (binary), HLAT = 010 (binary), LRAM = 1 (binary),
and LDEV = 1 (binary) for the last device
— DQ Bus: At the same time in cycle A, DQ[71:0] must be driven with the 72-bit data to be compared.
— Command Bus: The host ASIC continues to drive CMDV HIGH and to apply Search command CMD[1:0] = “10”. CMD[5:2]
— DQ Bus: The DQ[71:0] continues to carry the search key to be compared.
must now be driven by the index of the comparand register pair for storing the search key presented on the DQ bus during
cycles A and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the
matching entry and hit flag (see page 27 for a description of SSR[0:7]). CMD[10:9] are don’t cares for this cycle.
72-bit Single Search for 1 device or cascade up to eight devices
Figure 6-8. Multiwidth Configurations Using CYNSE10512 as an Example
64K
16K
8K
72
144
Upper half
(Array 0)
288
CONFIDENTIAL
PRELIMINARY
64K
16K
8K
72
144
Lower half
(Array 1)
288
CYNSE10512
CYNSE10256
CYNSE10128
Page 60 of 153
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