CYNSE10128-083FGCI CYPRESS [Cypress Semiconductor], CYNSE10128-083FGCI Datasheet - Page 126

• Manufacturer Part Number: CYNSE10128-083FGCI
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-02069 Rev. *F
M = 25 for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128
TLSZ = 10 (binary), HLAT = 010 (binary), LRAM = 0 (binary), LDEV = 0 (binary)
SADR[M:0]
CMD[10:2]
CMD[1:0]
CLK2X
PHS_L
ALE_L
CMDV
WE_L
OE_L
CE_L
ACK
SSV
SSF
DQ
DQ[71:0]
CMD[10:0], CMDV
SSF, SSV
z
z
z
z
z
z
z
z
Figure 6-67. Hardware Diagram of 31 Devices Using Four Blocks
Figure 6-68. SRAM Read of Device #0 in a Bank of 31 Devices
cycle
Address
Read
1
A B
00
cycle
2
cycle
BHO[2]
BHO[2]
BHI[2]
3
CONFIDENTIAL
BHO[2]
BHO[2]
PRELIMINARY
Block of 8 Ayama 10000s Block 2
Block of 8 Ayama 10000s Block 0
Block of 8 Ayama 10000s Block 1
Block of 7 Ayama 10000s Block 3
BHI[2]
BHI[2]
BHI[2]
cycle
4
(devices 16–23)
(devices 24–30)
cycle
(devices 8–15)
(devices 0–7)
5
BHO[1]
BHO[1]
BHI[1]
BHO[1]
cycle
6
BHO[1]
BHI[1]
BHI[1]
BHI[1]
Address
cycle
7
0
0
1
cycle
8
BHO[0]
z
z
z
z
BHO[0]
BHO[0]
0
BHO[0]
BHI[0]
BHI[0]
BHI[0]
BHI[0]
cycle
DQ driven by the selected Ayama 10000
9
1
cycle
GND
GND
GND
10
0
SRAM
z
CYNSE10512
CYNSE10256
CYNSE10128
Page 126 of 153
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