CYNSE10128-083FGCI CYPRESS [Cypress Semiconductor], CYNSE10128-083FGCI Datasheet - Page 42

• Manufacturer Part Number: CYNSE10128-083FGCI
• Manufacturer: CYPRESS [Cypress Semiconductor]

5.6
If the CLK_MODE pin is LOW, Ayama 10000 receives the CLK2X and PHS_L signals. It uses the PHS_L signal to divide CLK2X
and generate an internal clock (CLK
only. Ayama 10000 uses an internal phase-locked loop (PLL) to lock the frequency of CLK1X and generates the internal clock
CLK, as shown in Figure 5-28. Also noted on these figures are cycles A and B. In CLK2X mode, cycle A begins on the rising edge
of CLK2X, when PHS_L is Low, and ends on the next rising edge. Cycle B begins on the rising edge of CLK2X when PHS_L is
High, and ends on the subsequent CLK2X rising edge. For CLK1X mode, the falling edge of CLK1X is considered the end of
cycle A, while the rising edge after that is considered the end of cycle B. Valid data must be available for the NSE at the END of
any cycle. Note. For the purpose of showing timing diagrams, all such diagrams in this document will be shown in CLK2X mode.
For a timing diagram in CLK1X mode, the following substitution can be made (see Figure 5-29).
Notes:
Document #: 38-02069 Rev. *F
6.
7.
8.
Use for CLK2X mode
Use for CLK1X mode
“CLK” is an internal clock signal.
Any reference to “CLK” cycles means one cycle of CLK.
Only supported in Non-Enhanced mode.
Clocks
Input Data
CLK
Input Data
CLK2X
PHS_L
CLK1X
CLK
[7]
[7]
CLK2X
PHS_L
CLK1X
“Cycle A End”
Figure 5-29. Ayama 10000 Clocks for All Timing Diagrams
“Cycle A End” “Cycle B End”
Figure 5-27. Ayama 10000 Clocks (CLK2X and PHS_L)
[6]
), as shown in Figure 5-27. If the CLK_MODE pin is HIGH, Ayama 10000 receives CLK1X
Figure 5-28. Ayama 10000 Clocks (CLK1X)
A
“Cycle B End”
A
CONFIDENTIAL
PRELIMINARY
B
B
CYNSE10512
CYNSE10256
CYNSE10128
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