MT41J128M8 MDTIC [Micon Design Technology Corporation], MT41J128M8 Datasheet - Page 114

• Manufacturer Part Number: MT41J128M8
• Description: 1Gb: x4, x8, x16 DDR3 SDRAM
• Manufacturer: MDTIC [Micon Design Technology Corporation]

Output Drive Strength
OUTPUT ENABLE/DISABLE
TDQS Enable
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_4.fm - Rev. D 8/1/08 EN
1. ODT is not allowed to be used.
2. The output data is no longer edge-aligned to the clock.
3. CL and CWL can only be six clocks.
The DRAM is not tested to check—nor does Micron warrant compliance with—normal
mode timings or functionality when the DLL is disabled. An attempt has been made to
have the DRAM operate in the normal mode where reasonably possible when the DLL
has been disabled; however, by industry standard, a few known exceptions are defined:
When the DLL is disabled, timing and functionality can vary from the normal operation
specifications when the DLL is enabled (see “DLL Disable Mode” on page 96). Disabling
the DLL also implies the need to change the clock frequency (see “Input Clock
Frequency Change” on page 99).
The DDR3 SDRAM uses a programmable impedance output buffer. The drive strength
mode register setting is defined by MR1[5, 1]. RZQ/7 (34Ω [NOM]) is the primary output
driver impedance setting for DDR3 SDRAM devices. To calibrate the output driver
impedance, an external precision resistor (RZQ) is connected between the ZQ ball and
V
The output impedance is set during initialization. Additional impedance calibration
updates do not affect device operation, and all data sheet timings and current specifica-
tions are met during an update.
To meet the 34Ω specification, the output drive strength must be set to 34Ω during
initialization. To obtain a calibrated output driver impedance after power-up, the DDR3
SDRAM needs a calibration command that is part of the initialization and reset proce-
dure.
The OUTPUT ENABLE function is defined by MR1[12], as shown in Figure 56 on
page 113. When enabled (MR1[12] = 0), all outputs (DQ, DQS, DQS#) function when in
the normal mode of operation. When disabled (MR1[12] = 1), all DDR3 SDRAM outputs
(DQ and DQS, DQS#) are tri-stated. The output disable feature is intended to be used
during I
leveling) only.
Termination data strobe (TDQS) is a feature of the x8 DDR3 SDRAM configuration,
which provides termination resistance (R
urations. TDQS is not supported in x4 or x16 configurations. When enabled via the mode
register (MR1[11]), the R
TDQS#. In contrast to the RDQS function of DDR2 SDRAM, TDQS provides the termina-
tion resistance R
by TDQS; thus, R
share the same ball. When the TDQS function is enabled via the mode register, the DM
function is not supported. When the TDQS function is disabled, the DM function is
provided, and the TDQS# ball is not used. The TDQS function is available in the x8 DDR3
SDRAM configuration only and must be disabled via the mode register for the x4 and x16
configurations.
SS
Q. The value of the resistor must be 240Ω ±1 percent.
DD
characterization of the READ current and during
TT
ON
only. The OUTPUT DATA STROBE function of RDQS is not provided
does not apply to TDQS and TDQS#. The TDQS and DM functions
TT
that is applied to DQS and DQS# is also applied to TDQS and
114
Micron Technology, Inc., reserves the right to change products or specifications without notice.
TT
), that may be useful in some system config-
1Gb: x4, x8, x16 DDR3 SDRAM
t
DQSS margining (write
©2006 Micron Technology, Inc. All rights reserved.
Operations