MT41J128M8 MDTIC [Micon Design Technology Corporation], MT41J128M8 Datasheet - Page 144

• Manufacturer Part Number: MT41J128M8
• Description: 1Gb: x4, x8, x16 DDR3 SDRAM
• Manufacturer: MDTIC [Micon Design Technology Corporation]

Figure 91: WRITE to READ (BC4 Mode Register Setting)
Command 1
DQS, DQS#
Address 3
DQ 4
CK#
CK
WRITE
Valid
T0
Notes:
NOP
T1
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2.
3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0 and the READ command at Ta0.
4. DI n = data-in for column n.
5. BC4 (fixed), WL = 5 (AL = 0, CWL = 5), RL = 5 (AL = 0, CL = 5).
t
data shown at T7.
WTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last write
NOP
T2
WL = 5
NOP
T3
NOP
T4
t WPRE
NOP
T5
DI
n
n + 1
DI
NOP
n + 2
T6
DI
n + 3
DI
t WPST
NOP
T7
Indicates A Break in
Time Scale
NOP
T8
t WTR 2
Transitioning Data
NOP
T9
Don’t Care
READ
Valid
Ta0