MT41J128M8 MDTIC [Micon Design Technology Corporation], MT41J128M8 Datasheet - Page 158

• Manufacturer Part Number: MT41J128M8
• Description: 1Gb: x4, x8, x16 DDR3 SDRAM
• Manufacturer: MDTIC [Micon Design Technology Corporation]

RESET
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_4.fm - Rev. D 8/1/08 EN
The RESET signal (RESET#) is an asynchronous signal that triggers any time it drops
LOW, and there are no restrictions about when it can go LOW. After RESET# goes LOW, it
must remain LOW for 100ns. During this time, the outputs are disabled, ODT (R
off (High-Z), and the DRAM resets itself. CKE should be brought LOW prior to RESET#
being driven HIGH. After RESET# goes HIGH, the DRAM must be reinitialized as though
a normal power up were executed (see Figure 109 on page 159). All refresh counters on
the DRAM are reset, and data stored in the DRAM is assumed unknown after RESET#
has gone LOW.
158
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1Gb: x4, x8, x16 DDR3 SDRAM
©2006 Micron Technology, Inc. All rights reserved.
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