MT41J128M8 MDTIC [Micon Design Technology Corporation], MT41J128M8 Datasheet - Page 35

• Manufacturer Part Number: MT41J128M8
• Description: 1Gb: x4, x8, x16 DDR3 SDRAM
• Manufacturer: MDTIC [Micon Design Technology Corporation]

Table 15:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN
I
Timing diagram example
CKE
External clock
t
t
t
t
t
t
CL
AL
CS#
Command inputs
Row/column addresses
Bank addresses
Data I/O
Output buffer DQ, DQS
ODT
Burst length
Active banks
Idle banks
Special notes
DD
CK
RC
RAS
RCD
RRD
RC
Test
I
DD
Measurement Conditions for I
Notes:
Bank address looping (0-to-1-to-2-to-3 . . . ) Bank address looping (0-to-1-to-2-to-3 . . . )
data switches after every clock cycle, which
I
1. For further definition of input switching, see Table 10 on page 29.
2. For further definition of data switching, see Table 11 on page 29.
Address input A10 must always be LOW
DD
Seamless read data burst (BL8): Output
means that read data is stable during
R0DDDR1DDDR2DDDR3DDDR4 . . .
4R: Burst Read Operating Current
HIGH between valid commands
Column addresses switching;
READ command/pattern:
Rx = READ from bank x
Figure 16 on page 36
Electrical Specifications – I
8 fixed (via MR0)
t
CK (MIN) I
falling DQS
Switching;
Disabled
CL I
HIGH
None
Off
On
n/a
n/a
n/a
n/a
n/a
n/a
All
0
DD
DD
DD
4R, I
35
DD
4W
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Seamless write data burst (BL8): Input data
I
DD
Address input A10 must always be LOW
W0DDDW1DDDW2DDDW3DDDW4 . . .
switches after every clock cycle, which
means that write data is stable during
4W: Burst Write Operating Current Notes
DD
HIGH between valid commands
Column addresses switching;
1Gb: x4, x8, x16 DDR3 SDRAM
WRITE command/pattern:
Specifications and Conditions
Wx = WRITE to bank x
8 fixed (via MR0)
DM always LOW
t
CK (MIN) I
falling DQS
Switching;
Disabled
CL I
HIGH
None
Off
On
n/a
n/a
n/a
n/a
n/a
All
–
0
DD
©2006 Micron Technology, Inc. All rights reserved.
DD
1
1
2