MT41J128M8 MDTIC [Micon Design Technology Corporation], MT41J128M8 Datasheet - Page 132

• Manufacturer Part Number: MT41J128M8
• Description: 1Gb: x4, x8, x16 DDR3 SDRAM
• Manufacturer: MDTIC [Micon Design Technology Corporation]

Figure 72: Nonconsecutive READ Bursts
Figure 73: READ (BL8) to WRITE (BL8)
DQS, DQS#
Command
Command 1
DQS, DQS#
Address
Address 2
CK#
DQ
CK
DQ 3
CK#
CK
Bank a,
READ
Col n
T0
READ
Bank,
Col n
T0
NOP
T1
Notes:
Notes:
NOP
T1
READ-to-WRITE command delay = RL + t CCD + 2 t CK - WL
NOP
T2
1. AL = 0, RL = 8.
2. DO n (or b) = data-out from column n (or column b).
3. Seven subsequent elements of data-out appear in the programmed order following DO n.
4. Seven subsequent elements of data-out appear in the programmed order following DO b.
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the READ command at T0, and
3. DO n = data-out from column, DI b = data-in for column b.
4. BL8, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
NOP
T2
the WRITE command at T6.
RL = 5
NOP
T3
NOP
T3
CL = 8
T4
NOP
NOP
T4
Bank a,
READ
Col b
T5
t RPRE
NOP
T5
T6
NOP
DO
n
n + 1
DO
WRITE
Bank,
Col b
T6
NOP
T7
n + 2
DO
n + 3
DO
T8
NOP
NOP
T7
DO
n + 4
n
DO
CL = 8
n + 5
DO
NOP
T9
NOP
T8
n + 6
DO
WL = 5
t RPST
T10
n + 7
NOP
DO
NOP
T9
NOP
T11
NOP
T10
t WPRE
T12
NOP
NOP
T11
DI
n
T13
NOP
n + 1
DI
DO
b
NOP
T12
n + 2
DI
T14
NOP
n + 3
t BL = 4 clocks
DI
Transitioning Data
NOP
n + 4
T13
DI
T15
NOP
n + 5
Transitioning Data
DI
n + 6
NOP
T14
DI
NOP
T16
n + 7
DI
t WPST
Don’t Care
NOP
Don’t Care
T15
NOP
T17
t WTR
t WR