MT41J128M8 MDTIC [Micon Design Technology Corporation], MT41J128M8 Datasheet - Page 168
MT41J128M8
Manufacturer Part Number
MT41J128M8
Description
1Gb: x4, x8, x16 DDR3 SDRAM
Manufacturer
MDTIC [Micon Design Technology Corporation]
Datasheet
1.MT41J128M8.pdf
(181 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT41J128M8BY-0 MS:B
Manufacturer:
MICRON
Quantity:
4 000
Company:
Part Number:
MT41J128M8DA-15
Manufacturer:
SIEMENS
Quantity:
1
Company:
Part Number:
MT41J128M8HX-125:D
Manufacturer:
MICRON
Quantity:
11 200
Company:
Part Number:
MT41J128M8HX-15E:D
Manufacturer:
MT
Quantity:
1 831
Company:
Part Number:
MT41J128M8HX-15E:D TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Company:
Part Number:
MT41J128M8HX-187E
Manufacturer:
IDT
Quantity:
75
Company:
Part Number:
MT41J128M8HX-187E:D TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Company:
Part Number:
MT41J128M8JP-107:G
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Company:
Part Number:
MT41J128M8JP-125:G
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT41J128M8JP-125:G
Manufacturer:
MICRON/美光
Quantity:
20 000
Company:
Part Number:
MT41J128M8JP-15E AIT:G
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Table 81:
Figure 116: Synchronous ODT
Symbol
ODTL on
ODTL off
ODTH4
ODTH8
t
t
AON
AOF
ODT
CKE
CK#
R
CK
TT
T0
Synchronous ODT Parameters
T1
ODT minimum HIGH time after ODT
Notes:
ODT turn-off relative to ODTL off
ODT turn-on relative to ODTL on
ODT synchronous turn-off delay
ODT synchronous turn-on delay
ODT minimum HIGH time after
assertion or WRITE (BC4)
T2
1. AL = 3; CWL = 5; ODTL on = WL = 6.0; ODTL off = WL - 2 = 6. R
AL = 3
Description
WRITE (BL8)
completion
completion
ODTH4 (MIN)
T3
ODTL on = CWL + AL - 2
T4
T5
Write registration with ODT
write registration with ODT
ODT registered HIGH, or
Completion of ODTL on
Completion of ODTL off
ODT registered HIGH
ODT registered HIGH
T6
Begins at
HIGH
HIGH
T7
t AON (MIN)
t AON (MAX)
T8
ODT registered LOW
ODT registered LOW
T9
AL = 3
R
R
Defined to
TT
TT
TT
_
_
R
_
R
ON
OFF
NOM
TT
TT
T10
_
_
ODTL off = CWL + AL - 2
±
OFF
±
ON
t
t
is enabled.
AON
AOF
R
TT
_
NOM
T11
Definition for All DDR3
See Table 53 on page 67
T12
CWL - 2
0.5
CWL + AL - 2
CWL + AL - 2
Speed Bins
t
CK ± 0.2
T13
6
4
t
t
Transitioning
CK
CK
t
CK
T14
t AOF (MIN)
t AOF (MAX)
Don’t Care
T15
Units
t
t
t
t
tCK
CK
CK
CK
CK
ps