MT41J128M8 MDTIC [Micon Design Technology Corporation], MT41J128M8 Datasheet - Page 135

• Manufacturer Part Number: MT41J128M8
• Description: 1Gb: x4, x8, x16 DDR3 SDRAM
• Manufacturer: MDTIC [Micon Design Technology Corporation]

PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_4.fm - Rev. D 8/1/08 EN
A DQS to DQ output timing is shown in Figure 79 on page 136. The DQ transitions
between valid data outputs must be within
DQS must also maintain a minimum HIGH and LOW time of
READ preamble, the DQ balls will either be floating or terminated depending on the
status of the ODT signal.
Figure 80 on page 137 shows the strobe-to-clock timing during a READ. The crossing
point DQS, DQS# must transition within ±
out has no timing relationship to clock, only to DQS, as shown in Figure 80 on page 137.
Figure 80 on page 137 also shows the READ preamble and postamble. Normally, both
DQS and DQS# are High-Z to save power (V
DQS is driven LOW and DQS# is HIGH for
The READ postamble,
During the READ postamble, DQS is driven LOW and DQS# is HIGH. When complete,
the DQ will either be disabled or will continue terminating depending on the state of the
ODT signal. Figure 85 on page 140 demonstrates how to measure
t
RPST, is one half clock from the last DQS, DQS# transition.
135
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t
t
DQSCK of the clock crossing point. The data
RPRE. This is known as the READ preamble.
t
DD
DQSQ of the crossing point of DQS, DQS#.
Q). Prior to data output from the DRAM,
1Gb: x4, x8, x16 DDR3 SDRAM
t
QSH and
©2006 Micron Technology, Inc. All rights reserved.
t
RPST.
t
QSL. Prior to the
Operations