MT41J128M8 MDTIC [Micon Design Technology Corporation], MT41J128M8 Datasheet - Page 7

• Manufacturer Part Number: MT41J128M8
• Description: 1Gb: x4, x8, x16 DDR3 SDRAM
• Manufacturer: MDTIC [Micon Design Technology Corporation]

1Gb: x4, x8, x16 DDR3 SDRAM
List of Figures
Figure 113: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 . . . . 165
Figure 114: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4. . . . . . . . . . . . . 166
Figure 115: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4. . . . . . . . . . . . . 166
Figure 116: Synchronous ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 117: Synchronous ODT (BC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 118: ODT During READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 119: Asynchronous ODT Timing with Fast ODT Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 120: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry . . . . 175
Figure 121: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit. . . . . . 177
Figure 122: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping . . . . . . . . . 179
Figure 123: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping. . . . . . . . . 180
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1Gb_DDR3_LOF.fm - Rev. D 8/1/08 EN
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