MT41J128M8 MDTIC [Micon Design Technology Corporation], MT41J128M8 Datasheet - Page 169

• Manufacturer Part Number: MT41J128M8
• Description: 1Gb: x4, x8, x16 DDR3 SDRAM
• Manufacturer: MDTIC [Micon Design Technology Corporation]

Figure 117: Synchronous ODT (BC4)
Command
ODT
CKE
CK#
R
CK
TT
NOP
T0
NOP
T1
Notes:
NOP
T2
1. WL = 7. R
2. ODT must be held HIGH for at least ODTH4 after assertion (T1).
3. ODT must be kept HIGH ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (T7).
4. ODTH is measured from ODT first registered HIGH to ODT first registered LOW or from the registration of the WRITE
5. Although ODTH4 is satisfied from ODT registered HIGH at T6, ODT must not go LOW before T11 as ODTH4 must also be
command with ODT HIGH to ODT registered LOW.
satisfied from the registration of the WRITE command at T7.
ODTH4
ODTL on = WL - 2
NOP
T3
TT
NOP
T4
_
NOM
is enabled. R
NOP
T5
NOP
T6
TT
t AON (MIN)
_
t AON (MAX)
WR
WRS4
ODTL off = WL - 2
T7
is disabled.
ODTH4 (MIN)
ODTL on = WL - 2
NOP
T8
R
TT
_
NOM
ODTH4
NOP
T9
t AOF (MAX)
t AOF (MIN)
NOP
T10
NOP
T11
t AON (MIN)
t AON (MAX)
NOP
T12
ODTLoff = WL - 2
NOP
T13
R
TT
_
NOM
NOP
T14
NOP
T15
Transitioning
NOP
T16
Don’t Care
t AOF (MIN)
t AOF (MAX)
NOP
T17