MT41J128M8 MDTIC [Micon Design Technology Corporation], MT41J128M8 Datasheet - Page 145

• Manufacturer Part Number: MT41J128M8
• Description: 1Gb: x4, x8, x16 DDR3 SDRAM
• Manufacturer: MDTIC [Micon Design Technology Corporation]

Figure 92: WRITE (BC4 OTF) to READ (BC4 OTF)
Command 1
DQS, DQS#
Address 3
DQ 4
CK#
CK
WRITE
Valid
T0
Notes:
NOP
T1
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2.
3. The BC4 OTF setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0 and the READ command
4. DI n = data-in for column n.
5. BC4, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
t
at Tn.
WTR controls the WRITE-to-READ delay to the same device and starts after
NOP
T2
WL = 5
NOP
T3
NOP
T4
t WPRE
NOP
T5
DI
n
n + 1
DI
NOP
n + 2
T6
DI
n + 3
DI
t WPST
t BL = 4 clocks
NOP
T7
NOP
T8
t
BL.
NOP
T9
Indicates A Break in
Time Scale
T10
NOP
t WTR 2
Transitioning Data
NOP
T11
READ
Valid
Tn
Don’t Care
RL = 5