MT41J128M8 MDTIC [Micon Design Technology Corporation], MT41J128M8 Datasheet - Page 118

• Manufacturer Part Number: MT41J128M8
• Description: 1Gb: x4, x8, x16 DDR3 SDRAM
• Manufacturer: MDTIC [Micon Design Technology Corporation]

SRT vs. ASR
DYNAMIC ODT
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_4.fm - Rev. D 8/1/08 EN
If the normal case temperature limit of 85°C is not exceeded, then neither SRT nor ASR is
required, and both can be disabled throughout operation. However, if the extended
temperature option of 95°C is needed, the user is required to provide a 2X refresh rate
during (manual) refresh and to enable either the SRT or the ASR to ensure self refresh is
performed at the 2X rate.
SRT forces the DRAM to switch the internal self refresh rate from 1X to 2X. Self refresh is
performed at the 2X refresh rate regardless of the case temperature.
ASR automatically switches the DRAM’s internal self refresh rate from 1X to 2X. However,
while in self refresh mode, ASR enables the refresh rate to automatically adjust between
1X to 2X over the supported temperature range. One other disadvantage with ASR is the
DRAM cannot always switch from a 1X to a 2X refresh rate at an exact case temperature
of 85°C. Although the DRAM will support data integrity when it switches from a 1X to a
2X refresh rate, it may switch at a lower temperature than 85°C.
Since only one mode is neccesary, SRT and ASR cannot be enabled at the same time.
The dynamic ODT (R
when a value is selected. This new DDR3 SDRAM feature enables the ODT termination
value to change without issuing an MRS command, essentially changing the ODT termi-
nation “on-the-fly.”
With dynamic ODT (R
to dynamic ODT (R
back to ODT (R
the R
dynamic ODT (R
ODTH8, and
Dynamic ODT is only applicable during WRITE cycles. If ODT (R
dynamic ODT (R
dent of one other. Dynamic ODT is not available during write leveling mode, regardless
of the state of ODT (R
Termination (ODT)” on page 160.
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value will be High-Z. Special timing parameters must be adhered to when
ADC.
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) is enabled: ODTL
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) at the completion of the WRITE burst. If R
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WR
) when beginning a WRITE burst and subsequently switches
) feature is defined by MR2[10, 9]. Dynamic ODT is enabled
) enabled, the DRAM switches from normal ODT (R
118
). For details on dynamic ODT operation, refer to “On-Die
Micron Technology, Inc., reserves the right to change products or specifications without notice.
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1Gb: x4, x8, x16 DDR3 SDRAM
and R
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©2006 Micron Technology, Inc. All rights reserved.
can be used indepen-
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) is disabled,
Operations
is disabled,
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