MT41J128M8 MDTIC [Micon Design Technology Corporation], MT41J128M8 Datasheet - Page 131

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MT41J128M8

Manufacturer Part Number
MT41J128M8
Description
1Gb: x4, x8, x16 DDR3 SDRAM
Manufacturer
MDTIC [Micon Design Technology Corporation]
Datasheet

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Figure 70: Consecutive READ Bursts (BL8)
Figure 71: Consecutive READ Bursts (BC4)
Command 1
DQS, DQS#
Command 1
DQS, DQS#
Address 2
Address 2
DQ 3
DQ 3
CK#
CK#
CK
CK
READ
Bank,
READ
Col n
Bank,
Col n
T0
T0
Notes:
Notes:
NOP
NOP
T1
T1
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ command at T0 and T4.
3. DO n (or b) = data-out from column n (or column b).
4. BL8, RL = 5 (CL = 5, AL = 0).
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BC4 setting is activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during READ command at T0 and T4.
3. DO n (or b) = data-out from column n (or column b).
4. BC4, RL = 5 (CL = 5, AL = 0).
t CCD
t CCD
NOP
NOP
T2
T2
RL = 5
RL = 5
NOP
NOP
T3
T3
READ
READ
Bank,
Col b
Bank,
Col b
T4
T4
t RPRE
t RPRE
NOP
NOP
T5
T5
DO
DO
n
n
n + 1
n + 1
DO
DO
NOP
NOP
T6
T6
n + 2
n + 2
DO
DO
RL = 5
RL = 5
t RPST
n + 3
n + 3
DO
DO
NOP
NOP
T7
T7
n + 4
DO
n + 5
DO
NOP
NOP
T8
T8
n + 6
DO
t RPRE
n + 7
DO
NOP
NOP
T9
T9
DO
DO
b
b
b + 1
b + 1
DO
DO
NOP
T10
T10
NOP
b + 2
b + 2
DO
DO
t RPST
b + 3
b + 3
DO
DO
NOP
NOP
T11
T11
b + 4
DO
b + 5
DO
NOP
T12
NOP
T12
Transitioning Data
Transitioning Data
b + 6
DO
t RPST
b + 7
DO
NOP
T13
T13
NOP
Don’t Care
Don’t Care
NOP
NOP
T14
T14

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