MT41J128M8 MDTIC [Micon Design Technology Corporation], MT41J128M8 Datasheet - Page 171

• Manufacturer Part Number: MT41J128M8
• Description: 1Gb: x4, x8, x16 DDR3 SDRAM
• Manufacturer: MDTIC [Micon Design Technology Corporation]

Figure 118: ODT During READs
DQS, DQS#
Command
Address
ODT
CK#
DQ
CK
R
TT
READ
Valid
T0
NOP
T1
Notes:
NOP
T2
1. ODT must be disabled externally during READs by driving ODT LOW. For example, CL = 6; AL = CL - 1 = 5; RL = AL +
CL = 11; CWL = 5; ODTL on = CWL + AL - 2 = 8; ODTL off = CWL + AL - 2 = 8. R
NOP
T3
NOP
T4
ODTL off = CWL + AL - 2
R
TT
_
NOM
RL = AL + CL
NOP
T5
NOP
T6
NOP
T7
NOP
T8
NOP
T9
t AOF (MIN)
t AOF (MAX)
NOP
T10
ODTL on = CWL + AL - 2
NOP
T11
DI
b
b + 1
DI
NOP
T12
TT
b + 2
DI
_
NOM
b + 3
DI
NOP
T13
is enabled. R
b + 4
DI
b + 5
DI
NOP
T14
b + 6
DI
b + 7
TT
DI
NOP
Transitioning
T15
_
WR
is a “Don’t Care.”
t AON (MAX)
NOP
T16
R
TT
_
NOM
Don’t Care
NOP
T17