MT41J128M8 MDTIC [Micon Design Technology Corporation], MT41J128M8 Datasheet - Page 176

• Manufacturer Part Number: MT41J128M8
• Description: 1Gb: x4, x8, x16 DDR3 SDRAM
• Manufacturer: MDTIC [Micon Design Technology Corporation]

Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_5.fm - Rev. D 8/1/08 EN
The DRAM’s ODT may exhibit either asynchronous or synchronous behavior during
power-down exit (PDX). This transition period occurs if the DLL is selected to be off
when in precharge power-down mode by setting MR0[12] to “0.” Power-down exit
begins
first registered HIGH.
on + 1
ODT assertion during power-down exit results in an R
t
t
down exit may result in an R
ODTL off ×
ODTL off ×
If the AL has a large value, the uncertainty of the R
because ODTL on and ODTL off are derived from the WL, and WL is equal to CWL + AL.
Figure 121 on page 177 shows three different cases:
• ODT C: asynchronous behavior before
• ODT B: ODT state changes during the transition period, with
• ODT A: ODT state changes after the transition period with synchronous response
AONPD (MIN) and ODTL on ×
AONPD (MAX) and ODTL on ×
ODTL off ×
t
AOFPD (MAX)
t
CK. The transition period is
t
ANPD prior to CKE first being registered HIGH, and it ends
t
t
CK +
CK +
t
CK +
t
t
AOF (MIN) or as late as the greater of
AOF (MAX). Table 83 on page 175 summarizes these parameters.
t
AOF (MIN) and ODTL off ×
t
ANPD is equal to the greater of ODTL off + 1
TT
176
change as early as the lesser of
t
t
CK +
CK +
t
ANPD plus
t
t
AON (MIN) or as late as the greater of
AON (MAX). ODT de-assertion during power-
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t
ANPD
t
XPDLL.
1Gb: x4, x8, x16 DDR3 SDRAM
t
CK +
TT
state becomes quite large. This is
TT
t
On-Die Termination (ODT)
AOF (MAX) greater than
t
AOFPD (MAX) and
change as early as the lesser of
t
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AOFPD (MIN) and
t
AOFPD (MIN) less than
t
t
CK or ODTL
XPDLL after CKE is