AMD-K6 AMD [Advanced Micro Devices], AMD-K6 Datasheet - Page 135

• Manufacturer Part Number: AMD-K6
• Description: AMD-K6 Processor
• Manufacturer: AMD [Advanced Micro Devices]

20695H/0—March 1998
Table 14. Input Pin Types
Chapter 5
A20M#
AHOLD
BF[2:0]
BOFF#
BRDY#
BRDYC#
CLK
EADS#
EWBE#
FLUSH#
HOLD
Notes:
1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and
2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and
3. FLUSH
4. BF[2:0] are sampled during the falling transition of RESET. They must meet a minimum setup time of 1.0 ms and a minimum hold
5. During the initial power-on reset of the processor, RESET must remain asserted for a minimum of 1.0 ms after CLK and V
6. During a warm reset, while CLK and V
7. BRDYC# is also sampled during the falling transition of RESET. If RESET is driven synchronously, BRDYC# must meet the specified
Name
hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.
hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must
remain asserted at least two clocks.
sampled on a specific clock edge, setup and hold times must be met the clock edge before the clock edge on which RESET is
sampled negated. If asserted asynchronously, FLUSH# must meet a minimum setup and hold time of two clocks relative to the
negation of RESET.
time of two clocks relative to the negation of RESET.
specification before it is negated.
prior to its negation.
hold time relative to the negation of RESET. If asserted asynchronously, BRDYC# must meet a minimum setup and hold time of
two clocks relative to the negation of RESET.
#
is also sampled during the falling transition of RESET and can be asserted synchronously or asynchronously. To be
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Clock
Type
CC
are within their specification, RESET must remain asserted for a minimum of 15 clocks
Note 2, 3
Note 1
Note 4
Note 7
Signal Descriptions
Note
INIT
KEN#
RESET
IGNNE#
INTR
INV
NA#
NMI
SMI#
STPCLK#
WB/WT#
Name
AMD-K6
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Type
®
Processor Data Sheet
Note 5, 6
Note 1
Note 2
Note 2
Note 1
Note 2
Note 1
Note
CC
reach
117