AMD-K6 AMD [Advanced Micro Devices], AMD-K6 Datasheet - Page 97

• Manufacturer Part Number: AMD-K6
• Description: AMD-K6 Processor
• Manufacturer: AMD [Advanced Micro Devices]

20695H/0—March 1998
5
5.1
Summary
Sampled
Chapter 5
Signal Descriptions
A20M# (Address Bit 20 Mask)
Input
running in Real mode. The assertion of A20M # causes the
processor to force bit 20 of the physical address to 0 prior to
accessing the cache or driving out a memory bus cycle. The
clearing of address bit 20 maps addresses that wrap above 1
Mbyte to addresses below 1 Mbyte.
The processor samples A20M # as a level-sensitive input on
every clock edge. The system logic can drive the signal either
s y n ch ro n o u s ly o r a s y n c h ro n o u s ly. I f i t i s a s s e r t e d
asynchronously, it must be asserted for a minimum pulse width
of two clocks.
The following list explains the effects of the processor sampling
A20M# asserted under various conditions:
A20M# is used to simulate the behavior of the 8086 when
Inquire cycles and writeback cycles are not affected by the
state of A20M#.
The assertion of A20M# in System Management Mode
(SMM) is ignored.
When A20M# is sampled asserted in Protected mode, it
causes unpredictable processor operation. A20M# is only
defined in Real mode.
To ensure that A20M# is recognized before the first ADS#
occurs following the negation of RESET, A20M# must be
sampled asserted on the same clock edge that RESET is
sampled negated or on one of the two subsequent clock
edges.
To ensure A20M# is recognized before the execution of an
instruction, a serializing instruction must be executed
between the instruction that asserts A20M# and the
targeted instruction.
Signal Descriptions
AMD-K6
®
Processor Data Sheet
79