AMD-K6 AMD [Advanced Micro Devices], AMD-K6 Datasheet - Page 142

• Manufacturer Part Number: AMD-K6
• Description: AMD-K6 Processor
• Manufacturer: AMD [Advanced Micro Devices]

AMD-K6
Idle
Address
Data
Data-NA# Requested
Pipeline Address
124
®
Processor Data Sheet
The processor does not drive the system bus in the Idle state
and remains in this state until a new bus cycle is requested. The
processor enters this state off the clock edge on which the last
BRDY# of a cycle is sampled asserted during the following
conditions:
In addition, the processor is forced into this state when the
system logic asserts RESET or BOFF#. The transition to this
state occurs on the clock edge on which RESET or BOFF# is
sampled asserted.
In this state, the processor drives ADS# to indicate the
beginning of a new bus cycle by validating the address and
control signals. The processor remains in this state for one clock
and unconditionally enters the Data state on the next clock
edge.
In the Data state, the processor drives the data bus during a
write cycle or expects data to be returned during a read cycle.
The processor remains in this state until either NA# or the last
BRDY# is sampled asserted. If the last BRDY# is sampled
asserted or both the last BRDY# and NA# are sampled asserted
on the same clock edge, the processor enters the Idle state. If
NA# is sampled asserted first, the processor enters the
Data-NA# Requested state.
If the processor samples NA# asserted while in the Data state
and the current bus cycle is not completed (the last BRDY# is
not sampled asserted), it enters the Data-NA# Requested state.
The processor remains in this state until either the last BRDY#
is sampled asserted or an internal pending cycle is requested. If
the last BRDY# is sampled asserted before the processor drives
a new bus cycle, the processor enters the Idle state (no internal
pending cycle is requested) or the Address state (processor has
a internal pending cycle).
In this state, the processor drives ADS# to indicate the
beginning of a new bus cycle by validating the address and
control signals. In this state, the processor is still waiting for the
current bus cycle to be completed (until the last BRDY# is
The processor is in the Data state
The processor is in the Data-NA# Requested state and no
internal pending cycle is requested
Preliminary Information
Bus Cycles
20695H/0—March 1998
Chapter 6