AMD-K6 AMD [Advanced Micro Devices], AMD-K6 Datasheet - Page 26

• Manufacturer Part Number: AMD-K6
• Description: AMD-K6 Processor
• Manufacturer: AMD [Advanced Micro Devices]

AMD-K6
Enhanced RISC86
Microarchitecture
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Processor Data Sheet
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Th e En h anc ed R I SC 8 6 mi c ro a rchi t e c t ure de f i ne s t h e
characteristics of the AMD-K6. The innovative RISC86
microarchitecture approach implements the x86 instruction set
by internally translating x86 instructions into RISC86
operations. These RISC86 operations were specially designed to
include direct support for the x86 instruction set while
observing the RISC performance principles of fixed length
encoding, regularized instruction fields, and a large register
set. The Enhanced RISC86 microarchitecture used in the
AMD-K6 enables higher processor core performance and
promotes straightforward extensibility in future designs.
Instead of directly executing complex x86 instructions, which
have lengths of 1 to 15 bytes, the AMD-K6 processor executes
the simpler and easier fixed-length RISC86 opcodes, while
maintaining the instruction coding efficiencies found in x86
programs.
Th e A MD -K 6 p ro c e s so r c o n t a i n s p ara l l el d e c o d e rs , a
centralized RISC86 operation scheduler, and seven execution
units that support superscalar operation—multiple decode,
execution, and retirement—of x86 instructions. These elements
are packed into an aggressive and highly efficient six-stage
pipeline.
Decoders. Decoding of the x86 instructions begins when the
on-chip instruction cache is filled. Predecode logic determines
the length of an x86 instruction on a byte-by-byte basis. This
p re d e c o d e i n fo r m a t i o n i s s t o re d , a l o n g w i t h t h e x 8 6
instructions, in the instruction cache, to be used later by the
decoders. The decoders translate on-the-fly, with no additional
latency, up to two x86 instructions per clock into RISC86
operations.
Note: In this chapter, “clock” refers to a processor clock.
The AMD-K6 processor categorizes x86 instructions into three
types of decodes—short, long and vector. The decoders process
either two short, one long, or one vector decode at a time. The
three types of decodes have the following characteristics:
Short decodes—x86 instructions less than or equal to seven
bytes in length
Long decodes—x86 instructions less than or equal to 11
bytes in length
Vector decodes—complex x86 instructions
Preliminary Information
Internal Architecture
20695H/0—March 1998
Chapter 2