AMD-K6 AMD [Advanced Micro Devices], AMD-K6 Datasheet - Page 189

• Manufacturer Part Number: AMD-K6
• Description: AMD-K6 Processor
• Manufacturer: AMD [Advanced Micro Devices]

20695H/0—March 1998
8
Figure 67. Cache Organization
Chapter 8
Interface Unit
System Bus
Cache Organization
RAM
RAM
Tag
The following sections describe the basic architecture and
resources of the AMD-K6 processor internal caches.
The performance of the AMD-K6 processor is enhanced by a
writeback level-one (L1) cache. The cache is organized as a
separate 32-Kbyte instruction cache and a 32-Kbyte data cache,
each with two-way set associativity (See Figure 67). The cache
line size is 32 bytes, and lines are prefetched from main memory
using an efficient, pipelined burst transaction. As the
instruction cache is filled, each instruction byte is analyzed for
instruction boundaries using predecode logic. Predecoding
annotates each instruction byte with information that later
enables the decoders to efficiently decode multiple instructions
simultaneously. Translation lookaside buffers (TLB) are also
used to translate linear addresses to physical addresses. The
instruction cache is associated with a 64-entry TLB while the
data cache is associated with a 128-entry TLB.
Tag
Way 0
Way 0
Pre-Decode Instruction Cache
32-Kbyte Instruction Cache
Cache Organization
32-Kbyte Data Cache
128-Entry TLB
64-Entry TLB
MESI
State
Bits
Bit
Tag
RA
Tag
RA
Way 1
Way 1
MESI
Bits
State
Bit
AMD-K6
®
Processor Data Sheet
Processor
Core
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