AMD-K6 AMD [Advanced Micro Devices], AMD-K6 Datasheet - Page 15

no-image

AMD-K6

Manufacturer Part Number
AMD-K6
Description
AMD-K6 Processor
Manufacturer
AMD [Advanced Micro Devices]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AMD-K6-2
Manufacturer:
AMD
Quantity:
20 000
Part Number:
AMD-K6-2/233AFR
Manufacturer:
AMD
Quantity:
20 000
Part Number:
AMD-K6-2/350AFR
Manufacturer:
AMD
Quantity:
20 000
Part Number:
AMD-K6-2/400AFR
Manufacturer:
SMC
Quantity:
4
Part Number:
AMD-K6-2/475ACK
Manufacturer:
CPGA
Quantity:
20 000
Part Number:
AMD-K6-2/533AFX
Manufacturer:
INTEL
Quantity:
37
Part Number:
AMD-K6-2/533AFX
Manufacturer:
AMD
Quantity:
20 000
20695H/0—March 1998
List of Tables
AMD-K6 Processor Family
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Execution Latency and Throughput of Execution
Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
General-Purpose Register Dword, Word, and Byte
Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Segment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Model-Specific Registers (MSRs) . . . . . . . . . . . . . . . . . . . . . . . . 37
Memory Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . 39
Application Segment Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
System Segment and Gate Types . . . . . . . . . . . . . . . . . . . . . . . . 47
Summary of Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . 48
Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
MMX Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Processor-to-Bus Clock Ratios. . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Input Pin Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Output Pin Float Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Input/Output Pin Float Conditions . . . . . . . . . . . . . . . . . . . . . . 118
Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Bus Cycle Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Special Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Bus-Cycle Order During Misaligned Transfers . . . . . . . . . . . . 128
A[4:3] Address-Generation Sequence During Bursts . . . . . . . 130
Bus-Cycle Order During Misaligned I/O Transfers . . . . . . . . . 135
Interrupt Acknowledge Operation Definition. . . . . . . . . . . . . 156
Encodings For Special Bus Cycles . . . . . . . . . . . . . . . . . . . . . . 158
Output Signal State After RESET . . . . . . . . . . . . . . . . . . . . . . 168
Register State After RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
PWT Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
PCD Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
CACHE# Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Data Cache States for Read and Write Accesses . . . . . . . . . . 182
Cache States for Inquiries, Snoops, Invalidation, and
Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Snoop Action. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Initial State of Registers in SMM . . . . . . . . . . . . . . . . . . . . . . . 195
SMM State-Save Area Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
SMM Revision Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
I/O Trap Dword Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 200
Preliminary Information
Part One
AMD-K6
®
Processor Data Sheet
xv
3

Related parts for AMD-K6