AMD-K6 AMD [Advanced Micro Devices], AMD-K6 Datasheet - Page 174

• Manufacturer Part Number: AMD-K6
• Description: AMD-K6 Processor
• Manufacturer: AMD [Advanced Micro Devices]

AMD-K6
Interrupt
Acknowledge
156
®
Processor Data Sheet
In response to recognizing the system’s maskable interrupt
(INTR), the processor drives an interrupt acknowledge cycle at
t h e n e x t i n s t r u c t i o n b o u n d a ry. D u r i n g a n i n t e r r u p t
acknowledge cycle, the processor drives a locked pair of read
cycles as shown in Figure 61 on page 157. The first read cycle is
not functional, and the second read cycle returns the interrupt
number on D[7:0] (00h–FFh). Table 23 shows the state of the
signals during an interrupt acknowledge cycle.
Table 23. Interrupt Acknowledge Operation Definition
The system logic can drive INTR either synchronously or
asynchronously. If it is asserted asynchronously, it must be
asserted for a minimum pulse width of two clocks. To ensure it
is recognized, INTR must remain asserted until an interrupt
acknowledge sequence is complete.
D/C#
M/IO#
W/R#
BE[7:0]#
A[31:3]
D[63:0]
Processor Outputs
Preliminary Information
Bus Cycles
First Bus Cycle
0000_0000h
(ignored)
Low
Low
Low
EFh
Interrupt number expected from interrupt
FEh (low byte enabled)
controller on D[7:0]
Second Bus Cycle
0000_0000h
Low
Low
Low
20695H/0—March 1998
Chapter 6