AMD-K6 AMD [Advanced Micro Devices], AMD-K6 Datasheet - Page 193

• Manufacturer Part Number: AMD-K6
• Description: AMD-K6 Processor
• Manufacturer: AMD [Advanced Micro Devices]

20695H/0—March 1998
Cache-Related Signals
8.4
Chapter 8
Cache Disabling
Table 29 describes how the CACHE# signal is driven based on
writeback cycles, the CI bit of TR12, unlocked memory reads,
and the PCD signal.
Table 29. CACHE# Signal Generation
Complete descriptions of the signals that control cacheability
and cache coherency are given on the following pages:
To completely disable all cache accesses, the CD and NW bits
must be set to 1 and the cache must be completely flushed.
There are two different methods for flushing the cache. The
first method relies on the system logic and the second relies on
software.
Writeback
CACHE#—page 90
EADS#—page 94
FLUSH#—page 97
HIT#—page 98
HITM#—page 98
INV—page 102
KEN#—page 103
PCD—page 107
PWT—page 109
WB/WT#—page 116
Cycle
1
0
0
0
0
0
0
0
0
Cache Organization
CI Bit of TR12
X
1
0
1
0
1
0
1
0
Memory Reads
Unlocked
X
1
1
0
0
1
1
0
0
AMD-K6
PCD Signal
High
High
High
High
Low
Low
Low
Low
X
®
Processor Data Sheet
CACHE#
High
High
High
High
High
High
High
Low
Low
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