AMD-K6 AMD [Advanced Micro Devices], AMD-K6 Datasheet - Page 35

• Manufacturer Part Number: AMD-K6
• Description: AMD-K6 Processor
• Manufacturer: AMD [Advanced Micro Devices]

20695H/0—March 1998
Figure 5. AMD-K6
2.6
Chapter 2
Centralized RISC86
Operation Scheduler
Execution Units
®
®
Processor Scheduler
The AMD-K6 processor contains seven execution units—store,
load, integer X, integer Y, multimedia, floating-point, and
branch condition. Each unit is independent and capable of
handling the RISC86 operations. Table 1 on page 18 details the
execution units, functions performed within these units,
operation latency, and operation throughput.
The store and load execution units are two-staged pipelined
designs. The store unit performs data writes and register
calculation for LEA/PUSH. Data memory and register writes
from stores are available after one clock. The load unit
performs data memory reads. Data is available from the load
unit after two clocks.
The I nte ger X executio n unit can operat e on a ll AL U
operations, multiplies, divides (signed and unsigned), shifts,
and rotates.
RISC86 #0
RISC86 #1
Internal Architecture
RISC86 Operation Buffer
From Decode Logic
RISC86 #2
RISC86 #3
AMD-K6
RISC86 Issue Buses
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Processor Data Sheet
17