AMD-K6 AMD [Advanced Micro Devices], AMD-K6 Datasheet - Page 29

• Manufacturer Part Number: AMD-K6
• Description: AMD-K6 Processor
• Manufacturer: AMD [Advanced Micro Devices]

20695H/0—March 1998
Figure 1. AMD-K6
2.3
Cache
Chapter 2
Interface
Socket 7
Bus
Level-One Dual-Port Data Cache (32 KByte)
Predecode
Logic
Cache, Instruction Prefetch, and Predecode Bits
®
Processor Block Diagram
Out-of-Order
Execution Engine
Load
Level-One Cache
Unit
Controller
Operation Issue
The writeback level-one cache on the AMD-K6 processor is
organized as a separate 32-Kbyte instruction cache and a
32-Kbyte data cache with two-way set associativity. The cache
line size is 32 bytes and lines are prefetched from main memory
using an efficient pipelined burst transaction. As the
instruction cache is filled, each instruction byte is analyzed for
instruction boundaries using predecoding logic. Predecoding
annotates each instruction byte with information that later
enables the decoders to efficiently decode multiple instructions
simultaneously.
The processor cache design takes advantage of a sectored
organization (see Figure 2 on page 12). Each sector consists of
64 bytes configured as two 32-byte cache lines. The two cache
lines of a sector share a common tag but have separate pairs of
MESI (Modified, Exclusive, Shared, Invalid) bits that track the
state of each cache line.
Six RISC86
Level-One Instruction Cache
(32 KByte + Predecode)
Store
Queue
Unit
Store
®
(Register) Unit
Integer X
Internal Architecture
Dual Instruction Decoders
128-Entry DTLB
16-Byte Fetch
x86 to RISC86
Four RISC86
(24 RISC86)
Scheduler
Decode
Buffer
Multimedia
Unit
Control Unit
Instruction
(Register) Unit
64-Entry ITLB
Integer Y
(8192-Entry BHT)
(16-Entry BTC)
(16-Entry RAS)
Branch Logic
AMD-K6
Floating-Point
Unit
®
Processor Data Sheet
(Resolving) Unit
Branch
11