UJA1061TW PHILIPS [NXP Semiconductors], UJA1061TW Datasheet - Page 12

• Manufacturer Part Number: UJA1061TW
• Description: Low speed CAN/LIN system basis chip
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
2004 Mar 22
Low speed CAN/LIN system basis chip
SDM = logic 0 represents the normal watchdog behaviour.
out of Start-up/Restart/Sleep
watchdog
trigger
V3: ON/OFF/cyclic
INH: HIGH/floating
watchdog: window
CAN: active/auto
EN: HIGH/LOW
SYSINH: HIGH
watchdog: time-out
V3: ON/OFF/cyclic
INH: HIGH/floating
NORMAL
Flash entry = disabled
LIN: active
CAN: active/auto
EN: HIGH/LOW
SYSINH: HIGH
V1: ON
init Normal mode
via SPI to Sleep with pending wake-up
LIN: active
FLASH
V1: ON
via mode sequence 111/001/111
AND (watchdog trigger too early
successful
OR interrupt ignored > 256 ms)]
OR wrong mode register code
AND Flash entry enabled
via SPI
Flash entry = disabled
init Normal mode
reset pulse at pin RSTN
OR watchdog overflow
successful
Flash entry enabled
init Flash mode
OR [SDM = logic 0
OR mode change
via SPI
user defined
via SPI
OR interrupt ignored > 256 ms)]
watchdog
wrong mode register code
trigger
reset pulse at pin RSTN
SDM = logic 0) > 128 ms
AND (watchdog overflow
RSTN driven LOW AND
(RSTN = HIGH AND
OR [SDM = logic 0
user defined
mode change
mode change
oscillator
via SPI
via SPI
fail
OR (watchdog OFF AND I V > I V1(min) with reset option)
Fig.3 Main state diagram UJA1061.
OR (RSTN = HIGH AND V1 undervoltage)
OR (watchdog time-out with reset option)
via SPI to Sleep with pending wake-up
(RSTN falling edge AND SDM = logic 0)
OR (t > 256 ms and SDM = logic 0)
OR (t > 256 ms AND SDM = logic 0)
OR (Wake-up with reset option)
OR (wrong mode register code
OR interrupt ignored > 256 ms
OR SPI clock count < OR > 16
long reset pulse at pin RSTN
OR RSTN = LOW > 256 ms
OR SPI clock count < OR > 16
OR wrong mode register code
wrong mode register code
reset pulse at pin RSTN
watchdog: time-out/OFF
SYSINH: HIGH/floating
AND SDM = logic 0)
AND mode change
V3: ON/OFF/cyclic
INH: HIGH/floating
watchdog: start-up
V3: ON/OFF/cyclic
INH: HIGH/floating
Flash entry disabled
V3: ON/OFF/cyclic
watchdog: start-up
RSTN falling edge
EN: HIGH/LOW
SYSINH: HIGH
SYSINH: HIGH
SYSINH: HIGH
V3: unchanged
watchdog: OFF
user defined
FAIL-SAFE
START-UP
STANDBY
INH: floating
RSTN: LOW
RESTART
INH: floating
LIN: off-line
LIN: off-line
LIN: off-line
LIN: off-line
CAN: auto
CAN: auto
CAN: auto
CAN: auto
EN: LOW
EN: LOW
EN: LOW
V1: OFF
V1: ON
V1: ON
V1: ON
12
long reset pulse at pin RSTN
watchdog
trigger
reset code = Wake-up out
reset pulse at pin RSTN
Flash entry =
RSTN forced LOW
disabled
watchdog time-out
recovered osc fail
OR V3 overload
mode change
user defined
Wake-up AND
OR Wake-up
of fall-safe
via SPI
V1 undervoltage > 256 ms)
RSTN forced LOW
RSTN = LOW > 256 ms)
Flash entry = disabled
mode change
RSTN externally forced
(V1 is active AND
OR (V1 OK AND
action
event
via SPI
V3: unchanged
INH: floating
falling edge
watchdog: time-out/OFF
SYSINH: HIGH/floating
V3: ON/OFF/cyclic
long reset pulse at pin RSTN
AND V1 undervoltage
INH: floating
LIN: off-line
CAN: auto
BAT and GND connected
EN: LOW
SLEEP
V1: OFF
INH: floating
RSTN: LOW
V1 is active
INH: floating
first time
V3: OFF
mce624
Objective specification
Normal/Standby/
Flash mode only
out of
UJA1061
Normal/Standby/
Flash mode only
out of