UJA1061TW PHILIPS [NXP Semiconductors], UJA1061TW Datasheet - Page 33

• Manufacturer Part Number: UJA1061TW
• Description: Low speed CAN/LIN system basis chip
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
6.14.2
The mode register has cyclic access during system
operation. Here the watchdog is defined and re-triggered
as well as the current mode of operation is selected.
Furthermore the global enable output (bit EN) as well as
the Software Development Mode (bit SDM) control bit are
defined here. Depending on the system requirements, the
CAN physical medium can be activated with any access to
the CAN Mode bit (CM).
Table 3 MOD - Mode register (address 00) bit description
2004 Mar 22
11 to 6
Low speed CAN/LIN system basis chip
15, 14
5 to 3
BIT
13
12
2
M
ODE REGISTER
SYMBOL
NWP[5:0] Nominal Watchdog
OM[2:0]
A1, A0
SDM
RRS
RO
register address
Read Register Select
Read Only
Period
Operating Mode
Software
Development Mode
DESCRIPTION
(4)
VALUE
001001
001100
010010
010100
011011
100100
101101
110011
110101
110110
001
010
100
101
111
011
00
1
0
1
0
1
0
33
select Mode register
read System Diagnosis register (DIAG)
read System Status register (STAT)
read selected register without writing to Mode register
read selected register and write to Mode register
Normal operating mode
Standby mode
Sleep mode
initializing Normal mode
Flash Programming mode; note 2
initializing Flash mode 1; note 3
no watchdog reset; no interrupt monitoring; no reset
monitoring; no transitions to Fail-safe mode; Fail-safe is
entered only with a V1-undervoltage condition longer than
256 ms
Normal watchdog, interrupt, reset monitoring and fail-safe
behaviour
mode (ms)
This register has to be written during system start-up within
256 ms after RSTN has become released (HIGH-level on
RSTN). Any write access is checked for proper watchdog
and system mode coding. If an illegal code is detected, this
access is ignored by the UJA1061 and a system reset is
forced according to the state diagram of the system
controller.
operating
Normal
16
32
40
48
56
64
72
80
4
8
mode (ms)
Standby
OFF
1024
2048
4096
160
320
640
20
40
80
(1)
FUNCTION
Programming
mode (ms)
Flash
1024
2048
4096
8192
160
320
640
20
40
80
Objective specification
UJA1061
Sleep mode
OFF
1024
2048
3072
4096
6144
8192
(ms)
160
320
640
(1)