UJA1061TW PHILIPS [NXP Semiconductors], UJA1061TW Datasheet - Page 6

• Manufacturer Part Number: UJA1061TW
• Description: Low speed CAN/LIN system basis chip
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
5
2004 Mar 22
n.c.
n.c.
TXDL
V1
RXDL
RSTN
INTN
EN
SDI
SDO
SCK
SCS
TXDC
RXDC
n.c.
TEST
INH/LIMP
WAKE
RTL
V2
CANH
CANL
GND
RTH
LIN
RTLIN
BAT14
n.c.
Low speed CAN/LIN system basis chip
SYMBOL
PINNING
PIN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
not connected
not connected
transmit data input to activate the LIN output drive; LOW = LIN-bus dominant;
HIGH = LIN-bus recessive
regulated supply voltage output for microcontroller; voltage is 5 V, 3.3 V, 3 V
or 2.5 V according to version
receive data output for reading data from the LIN-bus; LOW when LIN-bus is
dominant; HIGH when LIN-bus is recessive
active LOW push-pull output used to reset the microcontroller; the UJA1061 also
monitors the voltage on pin RSTN for any clamping situation (fail-safe)
active LOW open-drain output used to interrupt the microcontroller; pin INTN is to
be wire-ANDed with other interrupt outputs within the ECU
push-pull enable output related to voltage regulator V1; active HIGH if the watchdog
is triggered successfully and a control bit is set; immediately pulled LOW with any
reset event (e.g. a watchdog overflow); full set/clear application access via SPI
while watchdog is served properly
SPI data input
SPI data output
SPI clock input
active LOW select input used to enable an SPI access
transmit data input that activates the CAN output driver; LOW = CAN-bus dominant;
HIGH = CAN-bus recessive
receive data output for reading data from the CAN-bus; LOW when CAN-bus is
dominant; HIGH when CAN-bus is recessive; output is continuously LOW upon a
wake-up event received via the CAN-bus
not connected
test pin; connect to ground in application
14 V battery related inhibit output for system extension, or ‘limp home’ output,
activated in Fail-safe mode (default floating)
42 V battery related local wake-up input
CAN termination resistor connection; in case of a CANL bus wire error this line is
terminated with a selectable impedance
regulated 5 V supply output reserved for CAN transceiver; an external buffer
capacitor connects to this pin
CAN-bus line; HIGH in dominant state and LOW in recessive state
CAN-bus line; LOW in dominant state and HIGH in recessive state
ground
CAN termination resistor connection; in case of a CANH bus wire error this line is
terminated with a selectable impedance
LIN-bus line; LOW when LIN-bus is dominant, HIGH when LIN-bus is recessive
LIN-bus termination resistor connection
14 V battery supply input
not connected
6
DESCRIPTION
Objective specification
UJA1061