UJA1061TW PHILIPS [NXP Semiconductors], UJA1061TW Datasheet - Page 19

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UJA1061TW

Manufacturer Part Number
UJA1061TW
Description
Low speed CAN/LIN system basis chip
Manufacturer
PHILIPS [NXP Semiconductors]
Datasheet

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Philips Semiconductors
2004 Mar 22
Low speed CAN/LIN system basis chip
RSTN externally
forced falling
(pin RSTN = LOW)
edge
START-UP
< 256 ms
t < 256 ms
Reset mode: 1 ms or 20 ms
reset threshold: HIGH
NORMAL
Reset mode: 20 ms
pin RSTN = HIGH
t > t (reset mode)
watchdog init OK
(1 ms or 20 ms)
WATCHDOG
Power-on
HIGH
reset
LOW
reset
wait
set
set
init
Fig.8 Reset state description.
OR (V3 overload AND Sleep mode)
OR V1 active AND V1 undervoltage
OR interrupt ignored
OR wrong mode register code
reset threshold: no change
watchdog too early/time-out
set reset threshold: HIGH
Reset mode: no change
set reset threshold: HIGH
set Reset mode: 20 ms
OR Flash entry enabled
set Reset mode: 20 ms
OR V1 current monitor
watchdog init OK
(pin RSTN = LOW)
OR wake-up event
t 256 ms
256 ms
19
256 ms
AND RSTN driven LOW)
(pin RSTN = HIGH
(pin RSTN = LOW)
undervoltage V1
> 128 ms
t > 256 ms
RESTART
< 256 ms
AND no
Reset mode: 20 ms
FAIL-SAFE
(here always 20 ms)
OR undervoltage V1
t > t (Reset mode)
pin RSTN = HIGH
WATCHDOG
t > 256 ms
HIGH
LOW
reset
reset
wait
set
set
init
oscillator
Objective specification
fail
(pin RSTN
= LOW)
UJA1061
256 ms
action
mce629
event

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