UJA1061TW PHILIPS [NXP Semiconductors], UJA1061TW Datasheet - Page 3

• Manufacturer Part Number: UJA1061TW
• Description: Low speed CAN/LIN system basis chip
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
1
1.1
1.2
2004 Mar 22
Excellent EMC performance
outside module pins
CAN/LIN-bus pins are short-circuit proof to the battery
(up to 60 V) and to ground
Battery and CAN/LIN-bus pins are protected against
transients that occur in an automotive environment
(ISO7637)
Software Development mode partly disabling of fail-safe
and watchdog functionality to ease software
development
Unique SPI readable device type identification
Small footprint HTSSOP32 package (body 6
with low thermal resistance.
12 V, 24 V and 42 V system support with low sleep
current (typical 50 A)
Support of 2.5, 3.0, 3.3 and 5.0 V microcontrollers with
automatic adaption of interface levels to
microcontrollers
Flexible, independent external regulator extension via
14 V battery related pin INH (enables fail-safe scalable
supply system)
Smart operating and power management modes
In-field Flash Programming mode
Cyclic wake-up capability in Standby and Sleep mode
Remote wake-up capability via CAN and LIN buses
Local WAKE port with cyclic supply feature
42 V battery related local wake-up input
42 V battery related high-side switch output to drive
external loads such as relays and wake-up switches
Interrupt output with 12 maskable interrupt sources:
– Interrupt service monitor
– One interrupt per watchdog period to prevent
Low speed CAN/LIN system basis chip
8 kV ESD protection (human body model) for the
FEATURES
microcontroller overloading; ensures predictable
software behaviour
General
System features
11 mm)
3
1.3
Extensive set of SPI-readable system diagnostics:
– Detection and detailed error reporting on CAN and
– TxD dominant and RxD recessive clamping as well
– Local ECU ground-shift detection with two selectable
– Over-temperature warning
– Battery monitoring to detect battery interrupt or a
– Signalling of potential RAM-retention errors due to
Programmable fail-safe coded window and time-out
watchdog with on-chip oscillator, guaranteeing
autonomous fail-safe system supervision
Fail-safe coded 16-bit SPI interface to microcontroller,
including chip-select pin for multiple SPI devices on the
same bus
Integrated fail-safe and system features:
– Rigorous error handling based on diagnostics
– 12 dedicated reset sources supporting different,
– Global enable pin for control of safety critical
– Limp home output signal for activating application
– Single SPI message; no assembly of multiple SPI
– Programmable active-low system reset with
– Fail-safe coded activation of Software Development
– 24-bit access-protected RAM can be used, for
LIN bus failures (e.g. shorts to GND/BAT, open bus
wires, etc.)
as RxD to TxD short detection to prevent bus
deadlocks
thresholds
chattering battery contact to store data before
microcontroller power down (e.g. to store seat
position)
low microcontroller V
history dependent, software start-up and diagnosis
hardware
hardware in case system enters Fail-safe mode
(e.g. switch on parking lights)
frames
detection of both clamped and open reset line to
prevent system deadlocks
mode and Flash mode
instance, for logging of cyclic problems.
Fail-safe features
CC
.
Objective specification
UJA1061