UJA1061TW PHILIPS [NXP Semiconductors], UJA1061TW Datasheet - Page 50

• Manufacturer Part Number: UJA1061TW
• Description: Low speed CAN/LIN system basis chip
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
6.14.12 S
This register is only accessible in Start-up mode after the first battery connection (BAT42) and allows special UJA1061
modes to be written only once. Another write access is possible only by removing the power from pin BAT42.
Table 13 SPE - Special Mode register (address 01) bit description
Note
1. Setting of ISDM is possible only via writing to the Special Mode register and is possible only once after supplying the
2004 Mar 22
Low speed CAN/LIN system basis chip
15, 14
6 to 0
BIT
BAT42 voltage to the UJA1061 for the first time. The access of the Special Mode register has to be executed before
the watchdog is initialized, that is before the first writing to the Mode register. Resetting is possible at any time via
the Mode register. A set ISDM flag disables all reset events caused by the UJA1061 during Normal mode (with the
exception of wrong mode register code resets), disables the interrupt time monitoring function during Normal mode,
and the Watchdog initialization time, the reset monitoring and the transitions to Fail Safe with the exception of a
V1-undervoltage longer than 256 ms. This bit is set automatically if pin TEST is forced to 7 V or higher during
power-on of the UJA1061 (Watchdog OFF Test mode or Device Level Test mode). Watchdog trigger failures result
only in the interrupt.
13
12
11
10
9
8
7
PECIAL
SYMBOL
ERREM
A1, A0
ISDM
RRS
LHM
RO
M
ODE REGISTER
register address
Read Register Select
Read Only
reserved
reserved
Initialize Software
Development Mode
Error-pin Emulation
Mode
Limp Home Mode
reserved
DESCRIPTION
VALUE
01
0
1
1
0
0
0
1
0
1
0
1
0
0
50
select Special Mode register
read the Interrupt Enable Feedback register (IEF)
read the Interrupt Feedback register (INT)
read the register selected by RRS without writing to the
Special Mode register
read the register selected by RRS and write to the Special
Mode register
reserved for future use; should always be set to logic 0 in
order to secure compatibility with future functions which will
be activated by a logic 1
reserved for future use; should always be set to logic 0 in
order to secure compatibility with future functions which will
be activated by a logic 1
no watchdog reset, no interrupt monitoring, no reset
monitoring, no transitions to Fail-safe mode, only during a
V1 undervoltage longer than 256 ms; note 1
normal watchdog interrupt, reset monitoring and fail-safe
behaviour
pin EN reflects the content of the CANFD register:
logic 1 if CANFD = 0000 (no error)
logic 0 if CANFD is not 0000 (error)
pin EN behaves as an enable pin (see Section 6.5.2)
IC-bit within System Configuration register is set entering
Fail-safe mode (‘limp home’ function)
IC-bit is cleared within System Configuration register when
entering Fail-safe mode (INH function)
reserved for future use; should always be set to logic 0 in
order to secure compatibility with future functions which will
be activated by a logic 1
FUNCTION
Objective specification
UJA1061