UJA1061TW PHILIPS [NXP Semiconductors], UJA1061TW Datasheet - Page 8

• Manufacturer Part Number: UJA1061TW
• Description: Low speed CAN/LIN system basis chip
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
6
6.1
The UJA1061 combines all peripheral functions around a
microcontroller within typical automotive body multiplexing
applications into one dedicated chip. The functions are:
6.2
The fail-safe system controller is the ‘heart’ of the
UJA1061 and is controlled mainly by the watchdog, which
is clocked directly via a dedicated, on-chip oscillator.
It handles the register configuration and controls all
internal functions of the UJA1061. The device status
information is collected and reflected to the
microcontroller. Also the reset and interrupt signals are
provided by the system controller.
The system controller is a state machine. The different
levels of operation provided are represented in Fig.3.
6.2.1
During severe fault situations the UJA1061 always enters
its Fail-safe mode (see also Fig.3). This mode has the
lowest possible system power consumption. These fault
situations are:
2004 Mar 22
Power supply for host microcontroller
Power supply for CAN physical layer
Switched BAT42 output
System reset
Watchdog with Window and Time-out modes
On-chip oscillator
Fault-tolerant CAN and LIN physical layers for serial
communication suitable for 12 and 42 V applications
SPI control interface
Local wake-up input
Inhibit output, or ‘limp home’ output
System Inhibit output port
Compatibility with 42 V power supply systems
Fail-safe behaviour.
On-chip oscillator failure (frequency too low). Fail-safe
mode is entered from any other mode immediately after
this failure is detected
Low speed CAN/LIN system basis chip
FUNCTIONAL DESCRIPTION
Introduction
Fail-safe system controller
F
AIL
-
SAFE MODE
8
The following events cause the system to exit the Fail-safe
mode if the on-chip oscillator is running correctly:
The UJA1061 restarts out of Fail-safe mode and enters
Start-up mode to give the application a new opportunity to
start. Regulator V1 starts again and the reset pulse will be
set to the long period (see Section 6.5.1).
6.2.2
Start-up mode is entered after a number of events that
result in a system reset (see Fig.3) and is the first
opportunity for the system to start-up. These events are:
Pin RSTN is clamped HIGH for more than 128 ms while
the UJA1061 tries to drive pin RSTN LOW. The
Fail-safe mode will be entered immediately out of any
other mode in which the UJA1061 tries to drive
pin RSTN LOW (Start-up, Standby or Sleep mode) after
detecting this failure
Pin RSTN is clamped LOW for more than 256 ms after
the UJA1061 has released the pin RSTN internally in
Start-up or in Restart mode
A falling edge on pin RSTN during the initialization
phase in Restart mode
No successful initialization of Normal mode within
256 ms after pin RSTN has become HIGH in Restart
mode whereby that the software-controlled Software
Development mode is not active
Wrong mode register code within Restart mode
Wrong SPI count within Restart mode
Low V1 regulator output for more than 256 ms due to a
too-high load or a short-circuit of V1 to ground in
Start-up mode
Low V1 regulator output directly after an
already-released pin RSTN in Restart mode.
Activity on the CAN-bus
Activity on the LIN-bus
Activity on pin WAKE.
The first battery and ground connection of the module
whereby the power supply V1 for the host
microcontroller becomes active for the first time. The
UJA1061 provides a Power-on reset for the system. As
this is the first connection of the battery, the UJA1061
has no indication of the reset length required by the host
microcontroller, therefore the long reset sequence is
chosen as default
S
TART
-
UP MODE
Objective specification
UJA1061