UJA1061TW PHILIPS [NXP Semiconductors], UJA1061TW Datasheet - Page 17

• Manufacturer Part Number: UJA1061TW
• Description: Low speed CAN/LIN system basis chip
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
6.5
The reset function of the UJA1061 offers two signals to
deal with reset events:
6.5.1
The system reset pin RSTN is a push-pull bidirectional
input/output. Pin RSTN is active LOW with selectable
pulse length upon the following events (see Fig.3):
All these events resulting in a reset have dedicated flags in
order to distinguish between the different events. The only
exception is the combination of the following two different
reset sources: the Power ON (first battery connection), or
pin BAT42 below Power-on reset threshold voltage and
pin RSTN externally forced LOW, falling edge event. The
reason is to have the same situation of the reset source
code after a Power-on reset and an external reset as an
emulator usually starts with a system reset. So during
development of the UJA1061 software with an emulator,
the UJA1061 will usually start-up with an external reset. If
2004 Mar 22
RSTN; the global ECU system reset
EN; a fail-safe global enable signal.
Power ON (first battery connection) or BAT42 below
Power-on reset threshold voltage
V1 Power ON (wake-up out of Sleep mode), indicated as
cyclic wake-up out of sleep
Low V1 supply
V1 current above threshold during Standby mode while
watchdog OFF behaviour is selected
V3 is down due to short-circuit condition during Sleep
mode
RSTN externally forced LOW, falling edge event
Successful preparation for Flash mode completed;
Flash mode can be entered now
Wake-up out of Standby mode via CAN, LIN or WAKE
while reset behaviour is selected; or wake-up out of
Sleep mode via CAN, LIN or WAKE
Wake-up event out of Fail-safe mode
Watchdog trigger failures (too early, too late, overflow,
time-out/not initialized in time, wrong code)
Illegal mode code via SPI applied
Interrupt not served within 256 ms.
Low speed CAN/LIN system basis chip
System reset
S
YSTEM RESET PIN
RSTN
17
the emulator is not used, the software starts-up with the
power-on code. Since the power-on code is a separate bit
(PWONS; Power-ON Status) in the System Status register
the microcontroller can distinguish between the Power-on
reset and the external reset. The UJA1061 will be reset
actively if pin RSTN is pulled LOW from external circuitry.
The UJA1061 will lengthen any reset event to 1 or 20 ms
in order to make sure that external hardware is reset
properly. After the first battery connection, a long
Power-on reset of 20 ms is provided after voltage V1 is
present. When started, the microcontroller can set the
Reset Length Control (RLC) flag within the UJA1061; this
allows the reset pulse to be shortened to 1 ms for future
reset events. With this flag set, all reset events are
shortened to 1 ms. Due to fail-safe behaviour, this flag will
be reset automatically (to the longer one) within Restart
mode, the first battery connection or with an
externally-applied falling edge at pin RSTN. With this
mechanism it is guaranteed that an erroneously-shortened
reset pulse will restart any microcontroller at least within
the second trial using the long reset pulse.
The behaviour of pin RSTN is shown in Fig.7. The duration
of t
the reset length). Once an external reset event has
occurred the system controller enters Start-up mode. Now
the watchdog starts monitoring pin RSTN to check
whether it is clamped or chattering. Finally Fail-safe mode
is entered in case pin RSTN is not properly released. The
reset state diagram is given in Fig.8.
If pin RSTN is released by the UJA1061 and the externally
lengthening is shorter than 256 ms, the watchdog
initialization starts with a time-out of 256 ms (start-up
time). If the watchdog initialization has been successful
within this start-up time, Normal or Flash mode will be
entered. If the start-up time expires, Restart mode is
entered providing a long reset pulse and resetting the
V1 undervoltage threshold to the HIGH level. Now with a
second system start and another 256 ms start-up time it is
possible to enter Normal mode. If this fails again, Fail-safe
mode is entered.
Furthermore, pin RSTN is monitored for a continuously
LOW clamping situation. Once the UJA1061 pulls
pin RSTN HIGH but pin RSTN level remains LOW for
more than 256 ms, the UJA1061 immediately enters
Fail-safe mode since this points to an application failure.
RSTL
depends on the setting of the RLC flag (defining
Objective specification
UJA1061