UJA1061TW PHILIPS [NXP Semiconductors], UJA1061TW Datasheet - Page 48

• Manufacturer Part Number: UJA1061TW
• Description: Low speed CAN/LIN system basis chip
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
6.14.11 P
This register allows the CAN and the LIN physical layer configuration to be read back.
Table 12 PLCF - Physical Layer Control Feedback register (address 11) bit description
2004 Mar 22
Low speed CAN/LIN system basis chip
15, 14
BIT
13
12
11
10
9
8
7
6
5
4
3
2
HYSICAL LAYER CONTROL FEEDBACK REGISTER
SYMBOL
A1, A0
CPCN
COTC
L42C
RRS
CRC
CTC
LSC
RO
register address
Read Register Select
Read Only
reserved
CAN Partial
Networking Control
CAN Off-line Time
Control
CAN Transmitter
Control
CAN Receiver
Control
reserved
reserved
LIN Slope Control
reserved
LIN 42 V Control
DESCRIPTION
VALUE
10
0
1
0
0
1
0
1
0
1
0
1
0
0
0
1
0
0
1
0
48
read the Physical Layer Control Feedback register (PLCF)
read the Physical Layer Control Feedback register without
writing to Physical Layer Control register
read the Physical Layer Control Feedback register and
write to Physical Layer Control register (previous setting
will be reflected)
reserved for future use; should always be set to logic 0 in
order to secure compatibility with future functions which will
be activated by a logic 1
allows Selective Sleep state to be entered; cleared
whenever the UJA1061 enters On-line or Active mode
no Selective Sleep mode allowed (default)
256 ms time until CAN falls into Off-line (400 ms after
Wake-up)
64 ms time until CAN falls into Off-line (400 ms after
Wake-up)
CAN transmitter is disabled; allows setting ‘listen only’
behaviour; set also due to a detected short at V2
CAN transmitter is enabled
TXD signal is forwarded to RXD during CAN
transmitter OFF
TXD signal is not forwarded to RXD during CAN transmitter
OFF
reserved for future use; should always be set to logic 0 in
order to secure compatibility with future functions which will
be activated by a logic 1
reserved for future use; should always be set to logic 0 in
order to secure compatibility with future functions which will
be activated by a logic 1
up to 10 kbit/s
up to 20 kbit/s
reserved for future use; should always be set to logic 0 in
order to secure compatibility with future functions which will
be activated by a logic 1
LIN termination supplied out of BAT42
LIN termination is always related to BAT14
FUNCTION
Objective specification
UJA1061