UJA1061TW PHILIPS [NXP Semiconductors], UJA1061TW Datasheet - Page 42

• Manufacturer Part Number: UJA1061TW
• Description: Low speed CAN/LIN system basis chip
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
6.14.7
This register allows the cause of an interrupt event to be read. The register is cleared upon read access and upon any
reset event. Hardware makes sure that no interrupt event is lost in case there is a new interrupt forced while reading the
register. The INTN pin is forced HIGH after reading the interrupt register for a defined period of time in order to make
sure that there is always an edge event guaranteed at the INTN pin.
The interrupts can be classified into two classes:
Table 8 INT - Interrupt register (address 01) bit description
2004 Mar 22
One in which the UJA1061 must react immediately due to timing-sensitive interrupts (SPI Clock CAN failure which
needs an immediate resend of a new SPI command, and BAT failure which needs immediate saving of critical data
into the non-volatile memory)
One which does not need an immediate reaction (OVERTEMP, Ground Shift, CAN and LIN failures, V2 and V3 failures
and the wake-ups via CAN, LIN and WAKE. These interrupts will be signalled in Normal Mode and Flash Mode via the
INTN pin to the microcontroller once per watchdog period (maximum).
Low speed CAN/LIN system basis chip
15, 14
BIT
13
12
11
10
9
8
7
6
5
4
3
I
NTERRUPT REGISTER
SYMBOL
V2V3FI
A1, A0
CANFI
BATFI
SPIFI
LINFI
RRS
WTI
GSI
OTI
RO
WI
register address
Read Register Select
Read Only
Watchdog Time-out
Interrupt
Over-Temperature
Interrupt
Ground Shift Interrupt
SPI clock count
Failure Interrupt
BAT Failure Interrupt
V2/V3 Failure
Interrupt
CAN Failure Interrupt
LIN Failure Interrupt
Wake-up Interrupt
DESCRIPTION
VALUE
01
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
42
read Interrupt register (INT)
read the Interrupt register without writing to Interrupt
Enable register
read the Interrupt register and write to Interrupt Enable
register
a watchdog overflow has occurred during Standby mode
no interrupt
the temperature warning limit has been exceeded or has
dropped below
no interrupt
the GND shift limit has been exceeded or has dropped
below
no interrupt
wrong number of CLK cycles (more than, or less than 16)
during SPI access; within Start-up and Restart modes, a
reset is performed instead of an interrupt
no interrupt; SPI access is ignored if wrong number of
cycles is applied (more than, or less than 16)
falling edge at SENSE forces an interrupt
no interrupt
short-circuit detected at V2 or V3 (details within system
status register 1)
no interrupt
CAN failure status has changed
no interrupt
LIN failure status has changed
no interrupt
a negative edge at WAKE has been detected
no edge
FUNCTION
Objective specification
UJA1061