MC68HC908AP16CFA MOTOROLA [Motorola, Inc], MC68HC908AP16CFA Datasheet - Page 104

• Manufacturer Part Number: MC68HC908AP16CFA
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Clock Generator Module (CGM)
Data Sheet
104
Addr.
$003A
$003B
$0036
$0037
$0038
$0039
NOTES:
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
PLL VCO Range Select
PLL Bandwidth Control
PLL Reference Divider
Register Name
PLL Control Register
PLL Multiplier Select
PLL Multiplier Select
Select Register
Register High
Register Low
Register
(PBWC)
Register
(PMSH)
(PMRS)
(PMDS)
(PMSL)
(PTCL)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Freescale Semiconductor, Inc.
Figure 8-2. CGM I/O Register Summary
For More Information On This Product,
PLLIE
AUTO
MUL7
VRS7
Bit 7
0
0
0
0
0
0
0
0
Go to: www.freescale.com
= Unimplemented
LOCK
MUL6
VRS6
PLLF
6
0
0
0
0
1
1
0
0
PLLON
MUL5
VRS5
ACQ
5
1
0
0
0
0
0
0
0
MUL4
VRS4
BCS
4
0
0
0
0
0
0
0
0
0
MUL11
PRE1
MUL3
VRS3
RDS3
R
MC68HC908AP Family — Rev. 2.5
3
0
0
0
0
0
0
0
= Reserved
MUL10
MUL2
RDS2
PRE0
VRS2
2
0
0
0
0
0
0
0
MUL9
MUL1
RDS1
VPR1
VRS1
1
0
0
0
0
0
0
0
MOTOROLA
VPR0
MUL8
MUL0
VRS0
RDS0
Bit 0
R
0
0
0
0
1