MC68HC908AP16CFA MOTOROLA [Motorola, Inc], MC68HC908AP16CFA Datasheet - Page 240

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MC68HC908AP16CFA

Manufacturer Part Number
MC68HC908AP16CFA
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
Serial Communications Interface
13.8.4 SCI Status Register 1
Data Sheet
240
Address:
PEIE — Receiver Parity Error Interrupt Enable Bit
SCI status register 1 (SCS1) contains flags to signal these conditions:
SCTE — SCI Transmitter Empty Bit
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
This read/write bit enables SCI error CPU interrupt
requests generated by the parity error bit, PE. (See
Register
This clearable, read-only bit is set when the SCDR transfers a
character to the transmit shift register. SCTE can generate an SCI
transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set,
SCTE generates an SCI transmitter CPU interrupt request. In normal
For More Information On This Product,
1 = SCI error CPU interrupt requests from PE bit enabled
0 = SCI error CPU interrupt requests from PE bit disabled
Transfer of SCDR data to transmit shift register complete
Transmission complete
Transfer of receive shift register data to SCDR complete
Receiver input idle
Receiver overrun
Noisy data
Framing error
Parity error
$0016
SCTE
Bit 7
1
Figure 13-12. SCI Status Register 1 (SCS1)
1.) Reset clears PEIE.
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= Unimplemented
TC
6
1
SCRF
5
0
IDLE
4
0
OR
MC68HC908AP Family — Rev. 2.5
3
0
NF
2
0
13.8.4 SCI Status
FE
1
0
MOTOROLA
Bit 0
PE
0

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