MC68HC908AP16CFA MOTOROLA [Motorola, Inc], MC68HC908AP16CFA Datasheet - Page 404

• Manufacturer Part Number: MC68HC908AP16CFA
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Low-Voltage Inhibit (LVI)
22.3.3 Polled LVI Operation
22.3.4 Forced Reset Operation
22.3.5 Voltage Hysteresis Protection
22.4 LVI Status Register
Data Sheet
404
Address:
Reset:
In applications that can operate at V
software can monitor V
register, the LVIPWRD bit must be at logic 0 to enable the LVI module,
and the LVIRSTD bit must be at logic 1 to disable LVI resets.
In applications that require V
enabling LVI resets allows the LVI module to reset the MCU when V
falls below the V
and LVIRSTD bits must be at logic 0 to enable the LVI module and to
enable LVI resets.
Once the LVI has triggered (by having V
will maintain a reset condition until V
voltage, V
continually entering and exiting reset if V
V
V
The LVI status register (LVISR) indicates if the V
detected below V
Read: LVIOUT
Write:
TRIPF1
HYS
Freescale Semiconductor, Inc.
For More Information On This Product,
.
$FE0F
Bit 7
. V
0
TRIPR1
TRIPR1
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= Unimplemented
TRIPF1
. This prevents a condition in which the MCU is
6
0
0
Figure 22-3. LVI Status Register
TRIPF1
is greater than V
DD
level. In the CONFIG1 register, the LVIPWRD
or V
5
0
0
by polling the LVIOUT bit. In the CONFIG1
REG
DD
to remain above the V
voltage was detected below V
4
0
0
TRIPF1
DD
DD
levels below the V
rises above the rising trip point
DD
DD
by the hysteresis voltage,
3
0
0
MC68HC908AP Family — Rev. 2.5
fall below V
is approximately equal to
DD
2
0
0
voltage was
TRIPF1
TRIPF1
TRIPF1
1
0
0
MOTOROLA
level,
), the LVI
TRIPF2
level,
Bit 0
0
0
DD
.