MC68HC908AP16CFA MOTOROLA [Motorola, Inc], MC68HC908AP16CFA Datasheet - Page 313

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MC68HC908AP16CFA

Manufacturer Part Number
MC68HC908AP16CFA
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
15.13 I/O Registers
15.13.1 SPI Control Register
MC68HC908AP Family — Rev. 2.5
MOTOROLA
Address: $0010
Three registers control and monitor SPI operation:
The SPI control register:
SPRIE — SPI Receiver Interrupt Enable Bit
Reset:
Read:
Write:
This read/write bit enables CPU interrupt requests generated by the
SPRF bit. The SPRF bit is set when a byte transfers from the shift
register to the receive data register. Reset clears the SPRIE bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
SPI status and control register (SPSCR)
Enables SPI module interrupt requests
Selects serial clock polarity and phase
SPI control register (SPCR)
SPI data register (SPDR)
Configures the SPI module as master or slave
Configures the SPSCK, MOSI, and MISO pins as open-drain
outputs
Enables the SPI module
SPRIE
Bit 7
0
Figure 15-13. SPI Control Register (SPCR)
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= Unimplemented
R
6
0
SPMSTR
5
1
CPOL
4
0
Serial Peripheral Interface Module (SPI)
CPHA
R
3
1
= Reserved
SPWOM
2
0
SPE
1
0
I/O Registers
Data Sheet
SPTIE
Bit 0
0
313

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