MC68HC908AP16CFA MOTOROLA [Motorola, Inc], MC68HC908AP16CFA Datasheet - Page 325

• Manufacturer Part Number: MC68HC908AP16CFA
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

16.5.7 Clock Synchronization
16.5.8 Handshaking
MC68HC908AP Family — Rev. 2.5
MOTOROLA
Since wired-AND logic is performed on SCL line, a high to low transition
on the SCL line will affect the devices connected to the bus. The devices
start counting their low period once a device’s clock has gone low, it will
hold the SCL line low until the clock high state is reached. However, the
change of low to high in this device clock may not change the state of the
SCL line if another device clock is still in its low period. Therefore the
synchronized clock SCL will be held low by the device which last
releases SCL to logic high. Devices with shorter low periods enter a high
wait state during this time. When all devices concerned have counted off
their low period, the synchronized SCL line will be released and go high,
and all devices will start counting their high periods. The first device to
complete its high period will again pull the SCL line low.
illustrates the clock synchronization waveforms.
The clock synchronization mechanism can be used as a handshake in
data transfer. A slave device may hold the SCL low after completion of
one byte data transfer and will halt the bus clock, forcing the master
clock into a wait state until the slave releases the SCL line.
Freescale Semiconductor, Inc.
For More Information On This Product,
SCL1
SCL2
Go to: www.freescale.com
SCL
Figure 16-3. Clock Synchronization
Internal counter reset
WAIT
Start counting high period
Multi-Master IIC Interface (MMIIC)
Multi-Master IIC Bus Protocol
Figure 16-3
Data Sheet
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